Status: Complete
The Arthur serial line interface is very closely modelled on the Beeb serial line interface. That in turn was modelled on the 6850 ACIA chip in the Beeb.
This document describes extensions to the RS423 serial line interface in RISC OS 2.00. These extensions are in addition to fixing some of the problems in Arthur 1.20, which are caused by a faulty ACIA chip.
0 => 9600 9 => 50 1 => 75 10 => 110 2 => 150 11 => 134.5 3 => 300 12 => 600 4 => 1200 13 => 1800 5 => 2400 14 => 3600 6 => 4800 15 => 72007 => 9600
SWI OS_SerialOp (&57)
Other input registers as determined by reason code
out: V=1 => R0 -> error
Other registers may return values, as determined by reason code
New state = (Old state AND R2) EOR R1
in: R1 = EOR mask
R2 = AND mask
out: R1 = old value of state
R2 = new value of state
The bits in the serial state have the following meanings:-
Bit Meaning --- ------- 0 Clear => No software flow-control (must rely on hardware handshaking).
Set => Use XON/XOFF flow-control protocol. The hardware will still
do CTS handshaking (ie if CTS goes low transmission will
stop), but we will not make RTS go low from our end.
1 Clear => If the ~DCD bit in the status register goes high, then cause
an RS423 event. Also, if a character is received when ~DCD is
high, then cause an RS423 event, and do not enter character
into buffer.
Set => Ignore the state of the ~DCD bit (apart from maintaining a
soft copy of this bit for the user to read). Note, however,
that both GTE and CMD chips prevent reception when the ~DCD
bit is high, and the GTE chip causes transmit problems when
this bit is high.
2 Clear => If the ~DSR bit in the status register is high, then do not
transmit characters.
Set => Ignore the state of the ~DSR bit (apart from maintaining a
soft copy of this bit for the user to read).
3 Clear => DTR bit in command register programmed to 1 (data terminal
ready).
Set => DTR bit in command register programmed to 0 (data terminal
not ready). Note that in this state, the ACIA cannot transmit
or receive characters. Any characters currently being
transmitted or received when this state is selected may be
garbled. The user should deselect this state before attempting
to transmit or receive again.
4..15 Undefined - do not modify these bits.
Bit Meaning
--- -------
16 Clear => Your transmission has not been stopped by the reception of an
XOFF character (always clear if XON/XOFF not being used).
Set => Your transmission has been stopped by the reception of an XOFF
character.
17 Clear => You intend the other end to be in the XON (enabled) state.
Set => You intend the other end to be in the XOFF (disabled) state.
When a character is received, and the buffer is nearly full (as
determined by OSBYTE 203), and XON/XOFF protocol is being used, then
this bit gets set, and on the next transmit interrupt an XOFF character
will be sent. When sufficient characters have been removed from the
input buffer to render it not nearly full, this bit is cleared and on
the next transmit interrupt an XON character is sent. Note that the
fact that this bit is set does not imply that the other end has
received an XOFF character yet.
18 Clear => the ~DCD bit in the status register is low, indicating that
carrier is present.
Set => the ~DCD bit in the status register is high, indicate absence
of carrier. In this state the ACIA receiver is disabled (and
on GTE chips transmission is affected, too)
19 Clear => the ~DSR bit in the status register is low, indicating a
'ready' state.
Set => the ~DSR bit in the status register is high, indicating a
'not-ready' state. If bit 2 of the serial state is clear, then
no characters will be transmitted in this state.
20 Clear => the ring indicator bit in IOC is low.
Set => the ring indicator bit in IOC is high.
21..31 Undefined - do not modify these bits.
R1 <> -1 => R1 determines new format
Bits 0,1 : 0 => 8 bit word
1 => 7 bit word
2 => 6 bit word
3 => 5 bit word
Bit 2 : 0 => 1 stop bit
1 => 2 stop bits
OR 1.5 stop bits if 5 bit word without parity
OR 1 stop bit if 8 bit word with parity
Bit 3 : 0 => parity disabled (no parity bit)
1 => parity enabled
Bits 4,5 : 0 => odd parity
1 => even parity
2 => parity bit always 1 on TX (ignored on RX)
3 => parity bit always 0 on TX (------""-----)
out: R1 = old format in bits 0..5 as above
in: R1 = length of break in centiseconds
out: R1 preserved
This call sets the ACIA to transmit a break, then waits in the foreground with IRQs on for R1 centiseconds before resetting it to normal. Note that any character being transmitted at the time the call is made may be garbled. After sending the break the remaining characters in the output buffer (if any) will be transmitted.
in: R1 = character to be sentout: R1 preserved
C=1 => character not sent (because buffer full)
This call puts a character in the RS423 output buffer, and reenables the transmit interrupt if it had previously been disabled by the MOS.
in: -out: C=0 => R1 = character read
C=1 => R1 preserved, no character read, input buffer empty
This call removes a character from the RS423 input buffer, if one is present. If removing a character leaves the input buffer with more free spaces than are specified by OSBYTE 203, then the other end is encouraged to start transmitting again - this may involve either reenabling RTS or the transmission of an XON character, depending on which protocol has been selected (see above).
Note that reception must have been enabled with FX2,2 (or FX2,1) before this call can be used.
R1 = 0..15 => set receive baud rate to this value (as for FX 7 or 8)
out: R1 = old receive baud rate, in range 0..15
Reason code R0=6 (Read/set transmit baud rate)
R1 = 0..15 => set transmit baud rate to this value (as for FX 7 or 8)
out: R1 = old transmit baud rate, in range 0..15