%!PS-Adobe-3.0 %%Creator: groff version 1.10 %%CreationDate: Wed Apr 14 20:58:18 1999 %%DocumentNeededResources: font Times-Bold %%+ font Times-Roman %%+ font Courier %%DocumentSuppliedResources: procset grops 1.10 0 %%Pages: 16 %%PageOrder: Ascend %%Orientation: Portrait %%EndComments %%BeginProlog %%BeginResource: procset grops 1.10 0 %!PS-Adobe-3.0 Resource-ProcSet /setpacking where{ pop currentpacking true setpacking }if /grops 120 dict dup begin /SC 32 def /A/show load def /B{0 SC 3 -1 roll widthshow}bind def /C{0 exch ashow}bind def /D{0 exch 0 SC 5 2 roll awidthshow}bind def /E{0 rmoveto show}bind def /F{0 rmoveto 0 SC 3 -1 roll widthshow}bind def /G{0 rmoveto 0 exch ashow}bind def /H{0 rmoveto 0 exch 0 SC 5 2 roll awidthshow}bind def /I{0 exch rmoveto show}bind def /J{0 exch rmoveto 0 SC 3 -1 roll widthshow}bind def /K{0 exch rmoveto 0 exch ashow}bind def /L{0 exch rmoveto 0 exch 0 SC 5 2 roll awidthshow}bind def /M{rmoveto show}bind def /N{rmoveto 0 SC 3 -1 roll widthshow}bind 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newpath 0 360 arc closepath }bind def /TM matrix def /DE{ TM currentmatrix pop translate scale newpath 0 0 .5 0 360 arc closepath TM setmatrix }bind def /RC/rcurveto load def /RL/rlineto load def /ST/stroke load def /MT/moveto load def /CL/closepath load def /FL{ currentgray exch setgray fill setgray }bind def /BL/fill load def /LW/setlinewidth load def /RE{ findfont dup maxlength 1 index/FontName known not{1 add}if dict begin { 1 index/FID ne{def}{pop pop}ifelse }forall /Encoding exch def dup/FontName exch def currentdict end definefont pop }bind def /DEFS 0 def /EBEGIN{ moveto DEFS begin }bind def /EEND/end load def /CNT 0 def /level1 0 def /PBEGIN{ /level1 save def translate div 3 1 roll div exch scale neg exch neg exch translate 0 setgray 0 setlinecap 1 setlinewidth 0 setlinejoin 10 setmiterlimit []0 setdash /setstrokeadjust where{ pop false setstrokeadjust }if /setoverprint where{ pop false setoverprint }if newpath /CNT countdictstack def userdict begin /showpage{}def }bind def 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/germandbls/agrave/aacute/acircumflex/atilde/adieresis/aring/ae/ccedilla /egrave/eacute/ecircumflex/edieresis/igrave/iacute/icircumflex/idieresis /eth/ntilde/ograve/oacute/ocircumflex/otilde/odieresis/divide/oslash /ugrave/uacute/ucircumflex/udieresis/yacute/thorn/ydieresis]def /Courier@0 ENC0/Courier RE/Times-Roman@0 ENC0/Times-Roman RE /Times-Bold@0 ENC0/Times-Bold RE %%EndSetup %%Page: 1 1 %%BeginPageSetup BP %%EndPageSetup /F0 19/Times-Bold@0 SF(ARM Instruction F)127.963 84 Q(ormats and T)-.475 E(imings)-.342 E/F1 10/Times-Bold@0 SF(Last r)72 117.6 Q -.15(ev)-.18 G (ised: 15th No).15 E -.1(ve)-.1 G(mber 1995).1 E/F2 10/Times-Roman@0 SF .157(The information included here is pro)72 133.2 R .157 (vided in good f)-.15 F .157(aith, b)-.1 F .157 (ut no responsibility can be accepted for an)-.2 F 2.657(yd)-.15 G(am-) -2.657 E .477(age or loss caused from the use of information contained \ within this document e)72 145.2 R -.15(ve)-.25 G 2.977(ni).15 G 2.977 (ft)-2.977 G .477(he author has been)-2.977 F (advised of the possibility of such loss.)72 157.2 Q .342 (This is not an of)72 172.8 R .342(\214cial document from ARM Ltd; in f) -.25 F .342(act other than a couple of nice people from ARM lim-)-.1 F .735(ited pointing out some of the corrections, the)72 184.8 R 3.235(yh) -.15 G -2.25 -.2(av e)-3.235 H .736 (no connection with this document at all. The)3.436 F 3.236(yd)-.15 G 3.236(on)-3.236 G(ot)-3.236 E(guarantee to ha)72 196.8 Q .3 -.15(ve f) -.2 H(ound all the mistak).15 E(es in this, so don')-.1 E 2.5(tb)-.18 G (lame them when you \214nd some more.)-2.5 E 1.501 (Corrections/amendments for this document w)72 212.4 R 1.501 (ould be most welcome. The)-.1 F 4.001(ys)-.15 G 1.5 (hould be reported to Robin)-4.001 F -.8(Wa)72 224.4 S (tts at the address belo).8 E -.65(w.)-.25 G 1.513 (Throughout this document, a `w)72 240 R 1.513 (ord' refers to 32 bits \(thats 4 bytes\) of memory)-.1 F 4.014(.I)-.65 G 4.014(fy)-4.014 G 1.514(ou don')-4.014 F 4.014(tl)-.18 G(ik)-4.014 E 4.014(et)-.1 G(his,)-4.014 E(tough.)72 252 Q 3.246(This document is a)72 267.6 R -.25(va)-.2 G 3.246(ilable in se).25 F -.15(ve)-.25 G 3.246 (ral forms.).15 F 3.246(An inde)8.246 F 5.746(xt)-.15 G 5.746(ot)-5.746 G 3.246(hem can be found it http://www)-5.746 F(.com-)-.65 E(lab)72 279.6 Q(.ox.ac.uk/oucl/users/robin.w)-.4 E .097 (atts/ARMinstrs/ on the W)-.1 F .097(orld W)-.8 F .097(ide W)-.4 F .097 (eb, or via anon)-.8 F .098(ymous FTP to ftp.com-)-.15 F(lab)72 291.6 Q (.ox.ac.uk in /tmp/Robin.W)-.4 E(atts/ARMinstrs/README.)-.8 E F1 2.5 (1. Pr)72 319.2 R(ocessor Modes)-.18 E F2 .87(ARM processors ha)72 334.8 R 1.17 -.15(ve a u)-.2 H .87(ser mode and a number of pri).15 F(vile) -.25 E .87(ged supervisor modes.)-.15 F .87(These are used as fol-)5.87 F(lo)72 346.8 Q(ws:)-.25 E 15.28(IRQ Entered)72 362.4 R (when an Interrupt Request \(IRQ\) is triggered.)2.5 E 16.39 (FIQ Entered)72 378 R(when a F)2.5 E (ast Interrupt Request \(FIQ\) is triggered.)-.15 E 13.05(SVC Entered)72 393.6 R(when a Softw)2.5 E(are Interrupt \(SWI\) is e)-.1 E -.15(xe)-.15 G(cuted.).15 E 7.51(Undef Entered)72 409.2 R 2.008 (when an Unde\214ned instruction is e)4.508 F -.15(xe)-.15 G 2.009 (cuted \(Not ARM 2 and 3, where SVC mode is).15 F(entered\).)107 421.2 Q 17.5(Abt Entered)72 436.8 R 2.331(when a memory access attempt is abort\ ed by the memory manager \(e.g. MEMC or)4.831 F .853 (MMU\), usually because an attempt is made to access non-e)107 448.8 R .853(xistent memory or to access memory)-.15 F(from an insuf)107 460.8 Q (\214ciently pri)-.25 E(vile)-.25 E (ged mode \(Not ARM 2 and 3, where SVC mode is entered\).)-.15 E (In each case the appropriate hardw)72 476.4 Q(are v)-.1 E (ector is also called.)-.15 E F1 2.5(2. Registers)72 504 R F2 .36 (The ARM 2 and 3 ha)72 519.6 R .66 -.15(ve 2)-.2 H 2.86(73).15 G 2.86 (2b)-2.86 G .36(it processor re)-2.86 F .36 (gisters, 16 of which are visible at an)-.15 F 2.86(yg)-.15 G -2.15 -.25 (iv e)-2.86 H 2.86(nt).25 G .36(ime \(which six-)-2.86 F(teen v)72 531.6 Q(aries according to the processor mode\).)-.25 E (These are referred to as R0-R15.)5 E(The ARM 6 and later ha)72 547.2 Q .3 -.15(ve 3)-.2 H 2.5(13).15 G 2.5(2b)-2.5 G(it processor re)-2.5 E (gisters, ag)-.15 E(ain 16 of which are visible at an)-.05 E 2.5(yg)-.15 G -2.15 -.25(iv e)-2.5 H 2.5(nt).25 G(ime.)-2.5 E .026(R15 has special \ signi\214cance. On the ARM 2 and 3, 24 bits are used as the program cou\ nter)72 562.8 R 2.527(,a)-.4 G .027(nd the remain-)-2.527 F .269(ing 8 \ bits are used to hold processor mode, status \215ags and interrupt mode\ s. R15 is therefore often referred)72 574.8 R(to as PC.)72 586.8 Q (R15 = PC = NZCVIFpp pppppppp pppppppp ppppMM)187.215 604.8 Q .55 (Bits 0-1 and 26-31 are kno)72 622.8 R .55 (wn as the PSR \(processor status re)-.25 F .55(gister\). Bits 2-25 gi) -.15 F .85 -.15(ve t)-.25 H .55(he address \(in w).15 F(ords\))-.1 E .138(of the instruction currently being fetched into the e)72 634.8 R -.15(xe)-.15 G .137(cution pipeline \(see belo).15 F .137 (w\). Thus instructions are only)-.25 F -2.15 -.25(ev e)72 646.8 T 2.5 (re).25 G -.15(xe)-2.65 G(cuted from w).15 E(ord aligned addresses.)-.1 E .4 LW 391.665 657.3 184.335 657.3 DL 15(MC)189.335 666.8 S (urrent processor mode)-15 E 391.665 671.3 184.335 671.3 DL 18.89(0U) 189.335 680.8 S(ser Mode)-18.89 E 18.89(1F)189.335 692.8 S (ast interrupt processing mode \(FIQ mode\))-19.04 E 18.89(2I)189.335 704.8 S(nterrupt processing mode \(IRQ mode\))-18.89 E 18.89(3S)189.335 716.8 S(upervisor mode \(SVC mode\))-18.89 E 391.665 721.3 184.335 721.3 DL 205.725 657.3 205.725 721.3 DL 391.665 657.3 391.665 721.3 DL 184.335 657.3 184.335 721.3 DL EP %%Page: 2 2 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-2-)282.17 48 Q .4 LW 370.275 76.5 205.725 76.5 DL 12.5(Name Meaning)210.725 86 R 370.275 90.5 205.725 90.5 DL 31.66(NN) 210.725 100 S -2.25 -.15(eg a)-31.66 H(ti).15 E .3 -.15(ve \215)-.25 H (ag).15 E 32.77(ZZ)210.725 112 S(ero \215ag)-32.77 E 32.21(CC)210.725 124 S(arry \215ag)-32.21 E 31.66(Vo)210.725 136 S -1.11(Ve)-31.66 G (r\215o)1.11 E 2.5<778d>-.25 G(ag)-2.5 E 35.55(II)210.725 148 S (nterrupt request disable)-35.55 E 33.32(FF)210.725 160 S (ast interrupt request disable)-33.47 E 370.275 164.5 205.725 164.5 DL 370.275 76.5 370.275 164.5 DL 205.725 76.5 205.725 164.5 DL 1.001 (R14, R14_FIQ, R14_IRQ, and R14_SVC are sometimes kno)72 181.6 R 1.002 (wn as `link' re)-.25 F 1.002(gisters due to their beha)-.15 F(viour)-.2 E(during the branch with link instructions.)72 193.6 Q .626(The ARM 6 a\ nd later processor cores support a 32 bit address space. Such processor\ s can operate in both)72 209.2 R .823 (26 bit and 32 bit PC modes. In 26 bit PC mode, R15 acts as on pre)72 221.2 R .824(vious processors, and hence code can)-.25 F .305 (only be run in the lo)72 233.2 R .305(west 64MBytes of the address spa\ ce. In 32 bit PC mode, all 32 bits of R15 are used as)-.25 F .625 (the program counter)72 245.2 R 3.125(.S)-.55 G .625(eparate status re) -3.125 F .626 (gisters are used to store the processor mode and status \215ags. These) -.15 F(are de\214ned as follo)72 257.2 Q(ws:)-.25 E (NZCVxxxx xxxxxxxx xxxxxxxx IFxMMMMM)201.47 275.2 Q .738 (Note that the bottom tw)72 293.2 R 3.238(ob)-.1 G .738 (its of R15 are al)-3.238 F -.1(wa)-.1 G .737 (ys zero in 32-bit modes \212 i.e. you can still only get w).1 F(ord-) -.1 E(aligned instructions. An)72 305.2 Q 2.5(ya)-.15 G (ttempts to write non-zeros to these bits will be ignored.)-2.5 E (The follo)72 320.8 Q(wing modes are currently de\214ned:)-.25 E 378.285 331.3 197.715 331.3 DL 29.17(MN)207.715 340.8 S 15.56(ame Meaning)-29.17 F 378.285 345.3 197.715 345.3 DL 13.89(00000 usr_26 26)202.715 354.8 R (bit PC User Mode)2.5 E 14.72(00001 \214q_26 26)202.715 366.8 R (bit PC FIQ Mode)2.5 E 14.445(00010 irq_26 26)202.715 378.8 R (bit PC IRQ Mode)2.5 E 13.335(00011 svc_26 26)202.715 390.8 R (bit PC SVC Mode)2.5 E 378.285 395.3 197.715 395.3 DL 13.89 (10000 usr_32 32)202.715 404.8 R(bit PC User Mode)2.5 E 14.72 (10001 \214q_32 32)202.715 416.8 R(bit PC FIQ Mode)2.5 E 14.445 (10010 irq_32 32)202.715 428.8 R(bit PC IRQ Mode)2.5 E 13.335 (10011 svc_32 32)202.715 440.8 R(bit PC SVC Mode)2.5 E 13.89 (10111 abt_32 32)202.715 452.8 R(bit PC Abt Mode)2.5 E 12.5 (11011 und_32 32)202.715 464.8 R(bit PC Und Mode)2.5 E 378.285 469.3 197.715 469.3 DL 280.215 331.3 280.215 469.3 DL 235.215 331.3 235.215 469.3 DL 378.285 331.3 378.285 469.3 DL 197.715 331.3 197.715 469.3 DL (Extrapolating from the abo)72 486.4 Q .3 -.15(ve t)-.15 H (able, it might be e).15 E(xpected that the follo)-.15 E(wing tw)-.25 E 2.5(om)-.1 G(odes are also de\214ned:)-2.5 E 377.17 496.9 198.83 496.9 DL 29.17(MN)208.83 506.4 S 15.56(ame Meaning)-29.17 F 377.17 510.9 198.83 510.9 DL 13.89(00111 abt_26 26)203.83 520.4 R(bit PC Abt Mode)2.5 E 12.5(01011 und_26 26)203.83 532.4 R(bit PC Und Mode)2.5 E 377.17 536.9 198.83 536.9 DL 281.33 496.9 281.33 536.9 DL 236.33 496.9 236.33 536.9 DL 377.17 496.9 377.17 536.9 DL 198.83 496.9 198.83 536.9 DL .677 (These are in f)72 550.4 R .677(act unde\214ned \(and if you)-.1 F/F1 10 /Times-Bold@0 SF(do)3.177 E F0 .677 (write 00111 or 01011 to the mode bits, the resulting chip state)3.177 F -.1(wo)72 562.4 S(n').1 E 3.062(tb)-.18 G 3.061(ew)-3.062 G .561 (hat you might e)-3.061 F .561(xpect \212 i.e. it w)-.15 F(on')-.1 E 3.061(tb)-.18 G 3.061(ea2)-3.061 G .561(6-bit pri)-3.061 F(vile)-.25 E .561(ged mode with the appropriate R13 and)-.15 F(R14 sw)72 574.4 Q (apped in\).)-.1 E(The follo)72 590 Q(wing table sho)-.25 E(ws which re) -.25 E(gisters are a)-.15 E -.25(va)-.2 G (ilable in which processor modes:).25 E 503.69 600.5 72.31 600.5 DL 12.5 (Mode Re)77.31 610 R(gisters a)-.15 E -.25(va)-.2 G(ilable).25 E 503.69 614.5 72.31 614.5 DL 16.38(USR R0)77.31 624 R 89.725<8a52>99.725 G 39.16 (14 R15)-89.725 F 377.59 614.5 377.59 628.5 DL 108.14 600.5 108.14 628.5 DL 108.14 628.5 72.31 628.5 DL 134.81 628.5 108.14 628.5 DL 154.81 628.5 134.81 628.5 DL 176.48 628.5 154.81 628.5 DL 224.26 628.5 176.48 628.5 DL 250.93 628.5 224.26 628.5 DL 304.26 628.5 250.93 628.5 DL 324.26 628.5 304.26 628.5 DL 377.59 628.5 324.26 628.5 DL 503.69 628.5 377.59 628.5 DL 19.72(FIQ R0)77.31 638 R 5<8a52>15 G 15(7R)-5 G 52.5 (8_FIQ \212)-15 F 18.05(R14_FIQ R15)45 F 377.59 628.5 377.59 642.5 DL 176.48 628.5 176.48 642.5 DL 108.14 628.5 108.14 642.5 DL 108.14 642.5 72.31 642.5 DL 134.81 642.5 108.14 642.5 DL 154.81 642.5 134.81 642.5 DL 176.48 642.5 154.81 642.5 DL 224.26 642.5 176.48 642.5 DL 250.93 642.5 224.26 642.5 DL 304.26 642.5 250.93 642.5 DL 324.26 642.5 304.26 642.5 DL 377.59 642.5 324.26 642.5 DL 503.69 642.5 377.59 642.5 DL 18.61 (IRQ R0)77.31 652 R 47.225<8a52>47.225 G 2.5(12 R13_IRQ)-47.225 F 5 <8a52>19.44 G 16.94(14_IRQ R15)-5 F 377.59 642.5 377.59 656.5 DL 250.93 642.5 250.93 656.5 DL 108.14 642.5 108.14 656.5 DL 108.14 656.5 72.31 656.5 DL 134.81 656.5 108.14 656.5 DL 154.81 656.5 134.81 656.5 DL 176.48 656.5 154.81 656.5 DL 224.26 656.5 176.48 656.5 DL 250.93 656.5 224.26 656.5 DL 304.26 656.5 250.93 656.5 DL 324.26 656.5 304.26 656.5 DL 377.59 656.5 324.26 656.5 DL 503.69 656.5 377.59 656.5 DL 16.38 (SVC R0)77.31 666 R 47.225<8a52>47.225 G 2.5(12 R13_SVC)-47.225 F 5 <8a52>17.21 G 14.71(14_SVC R15)-5 F 377.59 656.5 377.59 670.5 DL 250.93 656.5 250.93 670.5 DL 108.14 656.5 108.14 670.5 DL 108.14 670.5 72.31 670.5 DL 134.81 670.5 108.14 670.5 DL 154.81 670.5 134.81 670.5 DL 176.48 670.5 154.81 670.5 DL 224.26 670.5 176.48 670.5 DL 250.93 670.5 224.26 670.5 DL 304.26 670.5 250.93 670.5 DL 324.26 670.5 304.26 670.5 DL 377.59 670.5 324.26 670.5 DL 503.69 670.5 377.59 670.5 DL 15.83 (ABT R0)77.31 680 R 47.225<8a52>47.225 G 2.5(12 R13_ABT)-47.225 F 5 <8a52>16.66 G 14.16(14_ABT R15)-5 F(\(ARM 6 and later only\))2.5 E 377.59 670.5 377.59 684.5 DL 250.93 670.5 250.93 684.5 DL 108.14 670.5 108.14 684.5 DL 108.14 684.5 72.31 684.5 DL 134.81 684.5 108.14 684.5 DL 154.81 684.5 134.81 684.5 DL 176.48 684.5 154.81 684.5 DL 224.26 684.5 176.48 684.5 DL 250.93 684.5 224.26 684.5 DL 304.26 684.5 250.93 684.5 DL 324.26 684.5 304.26 684.5 DL 377.59 684.5 324.26 684.5 DL 503.69 684.5 377.59 684.5 DL 14.17(UND R0)77.31 694 R 47.225<8a52>47.225 G 2.5 (12 R13_UND)-47.225 F 5<8a52>15 G 12.5(14_UND R15)-5 F (\(ARM 6 and later only\))2.5 E 503.69 698.5 72.31 698.5 DL 377.59 684.5 377.59 698.5 DL 250.93 684.5 250.93 698.5 DL 108.14 684.5 108.14 698.5 DL 503.69 600.5 503.69 698.5 DL 72.31 600.5 72.31 698.5 DL .238 (There are six status re)72 715.6 R .239(gisters on the ARM6 and later \ processors. One is the current processor status re)-.15 F(gister)-.15 E 2.365(\(CPSR\) and holds information about the current state of the pro\ cessor)72 727.6 R 4.865(.T)-.55 G 2.365(he other \214v)-4.865 F 4.865 (ea)-.15 G 2.365(re the sa)-4.865 F -.15(ve)-.2 G(d).15 E EP %%Page: 3 3 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-3-)282.17 48 Q .041(processor status re)72 84 R .041(gisters \(SPSRs\): there is one of these for each pri)-.15 F(vile) -.25 E .042(ged mode, to hold information about)-.15 F (the state the processor must be returned to when e)72 96 Q (xception handling in that mode is complete.)-.15 E(These re)72 111.6 Q (gisters are set and read using the MSR and MRS instructions respecti) -.15 E -.15(ve)-.25 G(ly).15 E(.)-.65 E/F1 10/Times-Bold@0 SF 2.5 (3. Pipeline)72 139.2 R F0(Rather than being a microcoded processor)72 154.8 Q 2.5(,t)-.4 G(he ARM is \(in k)-2.5 E (eeping with its RISCness\) entirely hardwired.)-.1 E 2.859 -.8(To s)72 170.4 T 1.259(peed e).8 F -.15(xe)-.15 G 1.259 (cution the ARM 2 and 3 ha).15 F 1.559 -.15(ve 3 s)-.2 H 1.259 (tage pipelines. The \214rst stage holds the instruction being).15 F .245(fetched from memory)72 182.4 R 2.745(.T)-.65 G .246 (he second starts the decoding, and the third is where it is actually e) -2.745 F -.15(xe)-.15 G .246(cuted. Due to).15 F .272 (this, the program counter is al)72 194.4 R -.1(wa)-.1 G .272 (ys 2 instructions be).1 F .272(yond the currently e)-.15 F -.15(xe)-.15 G .272(cuting instruction. \(This must be).15 F(tak)72 206.4 Q (en account of when calculating of)-.1 E (fsets for branch instructions\).)-.25 E .19 (Because of this pipeline, 2 instruction c)72 222 R .19(ycles are lost \ on a branch \(as the pipeline must re\214ll\). It is therefore)-.15 F (often preferable to mak)72 234 Q 2.5(eu)-.1 G (se of conditional instructions to a)-2.5 E -.2(vo)-.2 G(id w).2 E (asting c)-.1 E(ycles. F)-.15 E(or e)-.15 E(xample:)-.15 E/F2 9 /Courier@0 SF(...)97 266 Q(CMP R0,#0)97 276 Q(BEQ over)97 286 Q (MOV R1,#1)97 296 Q(MOV R2,#2)97 306 Q(over)72 316 Q(...)97 326 Q F0 (can be more ef)72 360 Q(\214ciently written as:)-.25 E F2(...)97 392 Q (CMP R0,#0)97 402 Q(MOVNE R1,#1)97 412 Q(MOVNE R2,#2)97 422 Q(...)97 432 Q F1 2.5(4. T)72 471.6 R(imings)-.18 E F0 (ARM instructions are timed in a mixture of S, N, I and C c)72 487.2 Q (ycles.)-.15 E(An S-c)72 502.8 Q(ycle is a c)-.15 E (ycle in which the ARM accesses a sequential memory location.)-.15 E (An N-c)72 518.4 Q(ycle is a c)-.15 E (ycle in which the ARM accesses a non-sequential memory location.)-.15 E .299(An I-c)72 534 R .299(ycle is a c)-.15 F .298 (ycle in which the ARM doesn')-.15 F 2.798(tt)-.18 G .298 (ry to access a memory location or to transfer a w)-2.798 F .298 (ord to or)-.1 F(from a coprocessor)72 546 Q(.)-.55 E 2.903(AC)72 561.6 S(-c)-2.903 E .403(ycle is a c)-.15 F .403(ycle in which a w)-.15 F .404 (ord is transferred between the ARM and a coprocessor on either the dat\ a)-.1 F -.2(bu)72 573.6 S 2.5(s\().2 G (for uncached ARMs\) or the coprocessor b)-2.5 E (us \(for cached ARMs\).)-.2 E .165(The dif)72 589.2 R .165 (ferent types of c)-.25 F .165 (ycle must all be at least as long as the ARM')-.15 F 2.665(sc)-.55 G .165(lock rating. The memory system can)-2.665 F (stretch them: with a typical DRAM system, this results in:)72 601.2 Q 21.5<834e>72 616.8 S(-c)-21.5 E .578(ycles being twice the minimum leng\ th \(essentially because DRAMs require a longer access pro-)-.15 F (tocol when the memory access is non-sequential\).)97 628.8 Q 21.5<8353> 72 644.4 S(-c)-21.5 E .068(ycles usually being the minimum length, b) -.15 F .068(ut occasionally being stretched to N-c)-.2 F .067 (ycle length \(when)-.15 F(you')97 656.4 Q .448 -.15(ve j)-.5 H .148 (ust mo).15 F -.15(ve)-.15 G 2.648(ds).15 G .148 (equentially from the last w)-2.648 F .148(ord of one memory "ro)-.1 F .149(w" to the \214rst of the ne)-.25 F .149(xt one)-.15 F/F3 7 /Times-Roman@0 SF(1)-4.1 I F0(\).)4.1 I .32 LW 144 664.4 72 664.4 DL/F4 5.6/Times-Roman@0 SF(1)82 672.92 Q/F5 8/Times-Roman@0 SF .095 (Memory controllers tend to use this simple strate)2 3.28 N .096 (gy: if an N-c)-.12 F .096 (ycle is requested, treat the access as not being)-.12 F .364 (in the same ro)72 686.2 R .364(w; if an S-c)-.2 F .364 (ycle is requested, treat the access as being in the same ro)-.12 F 2.363(wu)-.2 G .363(nless it is ef)-2.363 F(fecti)-.2 E -.12(ve)-.2 G .363(ly the).12 F .021(last w)72 696.2 R .021(ord in the ro)-.08 F 2.021 (w\()-.2 G .022(which can be detected quickly\). The net result is that) -2.021 F/F6 8/Times-Bold@0 SF(some)2.022 E F5(S-c)2.022 E .022 (ycles will last the same time)-.12 F 1.024(as an N-c)72 706.2 R 1.024 (ycle; if I remember correctly)-.12 F 3.024(,o)-.52 G 3.024(na)-3.024 G 3.024(nA)-3.024 G 1.023(rchimedes these are S-c)-3.024 F 1.023 (ycle accesses to an address which is)-.12 F(di)72 716.2 Q 1.195(visibl\ e by 16. The practical consequences of this for Archimedes code are: \(\ a\) that about 1 in 4 S-c)-.2 F(ycles)-.12 E .29(becomes an N-c)72 726.2 R .29(ycle, since for this purpose, all addresses are w)-.12 F .29 (ord addresses and so di)-.08 F .29(visible by 4; \(b\) that it is)-.2 F EP %%Page: 4 4 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-4-)282.17 48 Q 21.5<8349>72 84 S 2.5(-a)-21.5 G (nd C-c)-2.5 E(ycles al)-.15 E -.1(wa)-.1 G (ys being the minimum length.).1 E -.4(Wi)72 99.6 S (th a typical SRAM system, all four types of c).4 E (ycle are typically the minimum length.)-.15 E 1.126(On the 8MHz ARM2 u\ sed in the Acorn Archimedes A440/1, an S \(sequential\) c)72 115.2 R 1.126(ycle is 125ns and an N)-.15 F .421(\(non-sequential\) c)72 127.2 R .421(ycle is 250ns. It should be noted that these timings are)-.15 F/F1 10/Times-Bold@0 SF(not)2.922 E F0(attrib)2.922 E .422 (utes of the ARM, b)-.2 F .422(ut of)-.2 F .071(the memory system. E.g.\ an 8MHz ARM2 can be connected to a static RAM system which gi)72 139.2 R -.15(ve)-.25 G 2.57(sa1).15 G .07(25ns N)-2.57 F -.15(cy)72 151.2 S 1.131(cle. The f).15 F 1.131 (act that the processor is rated at 8MHz simply means that it isn')-.1 F 3.631(tg)-.18 G 1.131(uaranteed to w)-3.631 F 1.131(ork if you)-.1 F (mak)72 163.2 Q 2.5(ea)-.1 G .3 -.15(ny o)-2.5 H 2.5(ft).15 G (he types of c)-2.5 E(ycle shorter than 125ns in length.)-.15 E .84 (Cached processors: All the information gi)72 178.8 R -.15(ve)-.25 G 3.34(ni).15 G 3.34(si)-3.34 G 3.34(nt)-3.34 G .839(erms of the clock c) -3.34 F .839(ycles seen by the ARM. These do)-.15 F .397(not occur at a\ constant rate: the cache control logic changes the source of the clock\ c)72 190.8 R .397(ycles presented to the)-.15 F (ARM when cache misses occur)72 202.8 Q(.)-.55 E(Generally)72 218.4 Q 3.468(,ac)-.65 G .968(ached ARM has tw)-3.468 F 3.468(oc)-.1 G .968 (lock inputs: the "f)-3.468 F .967 (ast clock" FCLK and the "memory clock" MCLK.)-.1 F .947 (When operating normally from cache, the ARM is clock)72 230.4 R .948 (ed at FCLK speed and all types of c)-.1 F .948(ycle are the)-.15 F .479 (minimum length: cache is ef)72 242.4 R(fecti)-.25 E -.15(ve)-.25 G .478 (ly a type of SRAM from this point of vie).15 F 1.778 -.65(w. W)-.25 H .478(hen a cache miss occurs,).65 F 1.204(the ARM')72 254.4 R 3.704(sc) -.55 G 1.205 (lock is synchronised to MCLK, then the cache line \214ll tak)-3.704 F 1.205(es place at MCLK speed \(taking)-.1 F .907(either N+3S or N+7S de\ pending on the length of cache lines in the processor in)72 266.4 R -.2 (vo)-.4 G(lv).2 E .906(ed\), then the ARM')-.15 F(s)-.55 E (clock is resynchronised back to FCLK.)72 278.4 Q .734 (While the memory access is taking place, the ARM is being clock)72 294 R .734(ed: ho)-.1 F(we)-.25 E -.15(ve)-.25 G 1.534 -.4(r, a).15 H 3.234 (ni).4 G .734(nput called NW)-3.234 F .735(AIT is)-1.2 F .253 (used to cause the ARM c)72 306 R .252(ycles in)-.15 F -.2(vo)-.4 G(lv) .2 E .252(ed not to do an)-.15 F .252(ything until the correct w)-.15 F .252(ord arri)-.1 F -.15(ve)-.25 G 2.752(sf).15 G .252(rom memory)-2.752 F 2.752(,a)-.65 G(nd)-2.752 E 1.595(usually not to do an)72 318 R 1.595 (ything while the remaining w)-.15 F 1.595(ords arri)-.1 F 1.895 -.15 (ve \()-.25 H 1.596(to a).15 F -.2(vo)-.2 G 1.596 (id getting further memory requests).2 F .298 (while the cache is still b)72 330 R .298(usy with the cache line re\ \214ll\). The situation is also complicated by the f)-.2 F .298 (act that the)-.1 F .454(cached ARM can be con\214gured either for FCLK\ and MCLK to be synchronous to each other \(so FCLK is)72 342 R .759 (an e)72 354 R .759(xact multiple of MCLK, and e)-.15 F -.15(ve)-.25 G .759(ry MCLK clock c).15 F .759 (ycle starts at just about the same time as an FCLK)-.15 F -.15(cy)72 366 S(cle\) or asynchronous \(in which case FCLK and MCLK c).15 E (ycles can ha)-.15 E .3 -.15(ve a)-.2 H .3 -.15(ny r).15 H (elationship to each other\).).15 E 1.03(All in all, the situation is t\ herefore quite complicated. An approximation to the beha)72 381.6 R 1.031(viour is that when a)-.2 F .948(cache line miss occurs, the c)72 393.6 R .948(ycle in)-.15 F -.2(vo)-.4 G(lv).2 E .948(ed tak)-.15 F .948 (es the cache line re\214ll time \(i.e. N+3S or N+7S\) in MCLK)-.1 F -.15(cy)72 405.6 S 1.447(cles, with N-c).15 F 1.447(ycles and S-c)-.15 F 1.447(ycles probably being stretched as described abo)-.15 F 1.748 -.15 (ve f)-.15 H 1.448(or DRAM, plus a fe).15 F(w)-.25 E 1.716(more c)72 417.6 R 1.716(ycles to allo)-.15 F 4.216(wf)-.25 G 1.715 (or the resynchronisation periods. F)-4.216 F 1.715(or an)-.15 F 4.215 (ym)-.15 G 1.715(ore details, you really need to get a)-4.215 F (datasheet for the processor in)72 429.6 Q -.2(vo)-.4 G(lv).2 E(ed.)-.15 E F1 2.5(5. Instructions)72 457.2 R F0 .026 (Each ARM instruction is 32 bits wide, and are e)72 472.8 R .027 (xplained in more detail belo)-.15 F 1.327 -.65(w. F)-.25 H .027 (or each instruction class we).5 F(gi)72 484.8 Q .3 -.15(ve t)-.25 H (he instruction bitmap, and an e).15 E (xample of the syntax used by a typical assembler)-.15 E(.)-.55 E .229 (It should of course be noted that the mnemonic syntax is not \214x)72 500.4 R .229(ed; it is a property of the assembler)-.15 F 2.729(,n)-.4 G .229(ot the)-2.729 F(ARM machine code.)72 512.4 Q F1 2.5(5.1. Condition) 72 540 R(Code)2.5 E F0 .451(The top nibble of e)72 555.6 R -.15(ve)-.25 G .452(ry instruction is a condition code, so e).15 F -.15(ve)-.25 G .452(ry single ARM instruction can be run condi-).15 F(tionally)72 567.6 Q(.)-.65 E .32 LW 144 710 72 710 DL/F2 8/Times-Roman@0 SF (occasionally w)72 720 Q(orth taking care to align code carefully to a) -.08 E -.16(vo)-.16 G(id this ef).16 E(fect and get some e)-.2 E (xtra performance.\))-.12 E EP %%Page: 5 5 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-5-)282.17 48 Q .4 LW 493.625 76.5 82.375 76.5 DL(Cond)291.375 86 Q(Instruction Bitmap)87.375 98 Q 17.225(No Cond) 133.445 F 52.18(Code Ex)2.5 F(ecutes if)-.15 E 493.625 102.5 82.375 102.5 DL/F1 9/Courier@0 SF(0000xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 112 Q F0 23.335(0E)23.335 G 54.14(Q\(Equal\) Z)-23.335 F F1 (0001xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 124 Q F0 23.335(1N)23.335 G (E\(Not Equal\))-23.335 E(~Z)39.14 E F1 (0010xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 136 Q F0 23.335(2C)23.335 G (S\(Carry Set\))-23.335 E(C)43.02 E F1 (0011xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 148 Q F0 23.335(3C)23.335 G (C\(Carry Clear\))-23.335 E(~C)33.03 E 493.625 152.5 82.375 152.5 DL F1 (0100xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 162 Q F0 23.335(4M)23.335 G 52.47(I\(MInus\) N)-23.335 F F1(0101xxxx xxxxxxxx xxxxxxxx xxxxxxxx) 87.375 174 Q F0 23.335(5P)23.335 G 58.57(L\(PLus\) ~N)-23.335 F F1 (0110xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 186 Q F0 23.335(6V)23.335 G (S\(oV)-23.335 E(er\215o)-1.11 E 2.5(wS)-.25 G 26.33(et\) V)-2.5 F F1 (0111xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 198 Q F0 23.335(7V)23.335 G (C\(oV)-23.335 E(er\215o)-1.11 E 2.5(wC)-.25 G 16.34(lear\) ~V)-2.5 F 493.625 202.5 82.375 202.5 DL F1(1000xxxx xxxxxxxx xxxxxxxx xxxxxxxx) 87.375 212 Q F0 23.335(8H)23.335 G 51.93(I\(HIgher\) C)-23.335 F(and ~Z) 2.5 E F1(1001xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 224 Q F0 23.335(9L) 23.335 G(S\(Lo)-23.335 E(wer or Same\))-.25 E(~C or Z)20.23 E F1 (1010xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 236 Q F0 22.225(AG)22.225 G (E\(Greater or equal\))-22.225 E 2.5(N=V)15 G F1 (1011xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 248 Q F0 22.5(BL)22.5 G (T\(Less Than\))-23.42 E 2.5(N=~)40.62 G(V)-2.5 E 493.625 252.5 82.375 252.5 DL F1(1100xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 262 Q F0 22.5(CG) 22.5 G(T\(Greater Than\))-22.5 E(\(N = V\) and ~Z)26.94 E F1 (1101xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 274 Q F0 22.225(DL)22.225 G (E\(Less or equal\))-22.225 E(\(N = ~V\) or Z)27.76 E F1 (1110xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 286 Q F0 22.78(EA)22.78 G (L\(Al)-22.78 E -.1(wa)-.1 G 47.12(ys\) T).1 F(rue)-.35 E F1 (1111xxxx xxxxxxxx xxxxxxxx xxxxxxxx)87.375 298 Q F0 23.055(FN)23.055 G (V\(Ne)-23.055 E -.15(ve)-.25 G 52.33(r\) F).15 F(alse)-.15 E 493.625 302.5 82.375 302.5 DL 493.625 76.5 493.625 302.5 DL 82.375 76.5 82.375 302.5 DL .469(In most assemblers, the condition code is inserted immedi\ ately after the mnemonic stub; omitting a condi-)72 319.6 R (tion code def)72 331.6 Q(aults to AL being used.)-.1 E 1.164 (HS \(Higher or Same\) and LO \(LOwer\) can be used as synon)72 347.2 R 1.165(yms for CS and CC \(respecti)-.15 F -.15(ve)-.25 G 1.165 (ly\) in some).15 F(assemblers.)72 359.2 Q(The conditions GT)72 374.8 Q 2.5(,G)-.74 G(E, L)-2.5 E 1.48 -.74(T, L)-.92 H 2.5(Er).74 G (efer to signed comparisons whereas HS, HI, LS, LO refer to unsigned.) -2.5 E(EORing a condition code with 1 gi)72 390.4 Q -.15(ve)-.25 G 2.5 (st).15 G(he opposite condition code.)-2.5 E .255(NB: ARM ha)72 406 R .555 -.15(ve d)-.2 H .254 (eprecated the use of the NV condition code \212 you are no).15 F 2.754 (ws)-.25 G .254(upposed to use MO)-2.754 F 2.754(VR)-.5 G(0,R0)-2.754 E 1.126(as a noop rather than MO)72 418 R 1.126(VNV R0,R0 as w)-.5 F 1.126 (as pre)-.1 F 1.126(viously recommended. Future processors may ha)-.25 F 1.426 -.15(ve t)-.2 H(he).15 E (NV condition code reused to do other things.)72 430 Q .023 (Instructions with f)72 445.6 R .023(alse conditions e)-.1 F -.15(xe) -.15 G .023(cute in 1S c).15 F .022 (ycle, and no time penalty is incurred by making an instruc-)-.15 F (tion conditional.)72 457.6 Q/F2 10/Times-Bold@0 SF 2.5(5.2. Data)72 485.2 R(Pr)2.5 E(ocessing Instructions)-.18 E F1 (xxxx000a aaaSnnnn ddddcccc ctttmmmm)72 510.8 Q(Register form)10.8 E (xxxx001a aaaSnnnn ddddrrrr bbbbbbbb)72 520.8 Q(Immediate form)10.8 E F0 -.8(Ty)72 548.4 S(pical Assembler Syntax:).8 E F1 16.2(MOV Rd,)115.2 580.4 R(#0)5.4 E(ADDEQS Rd, Rn, Rm, ASL Rc)115.2 590.4 Q 5.4(ANDEQ Rd,) 115.2 600.4 R(Rn, Rm)5.4 E 10.8(TEQP Pn,)115.2 610.4 R(#&80000000)5.4 E 16.2(CMP Rn,)115.2 620.4 R(Rm)5.4 E F0(Combine contents of Rn with Op2,\ under operation a, placing the results in Rd.)72 648 Q .352(If the re) 72 663.6 R .353(gister form is used, then Op2 is set to be the contents\ of Rm shifted according to t as belo)-.15 F 4.153 -.65(w. I)-.25 H 2.853(ft).65 G(he)-2.853 E(immediate form is used, then Op2 = #b, R)72 675.6 Q(OR #2r)-.4 E(.)-.55 E EP %%Page: 6 6 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-6-)282.17 48 Q .4 LW 427.825 76.5 148.175 76.5 DL 19.86(tA)160.535 86 S 61.75(ssembler Interpretation)-19.86 F 427.825 90.5 148.175 90.5 DL 12.5(000 LSL)153.175 100 R 74.8(#c Logical)2.5 F (Shift Left)2.5 E 12.5(001 LSL)153.175 112 R 73.13(Rc Logical)2.5 F (Shift Left)2.5 E 12.5(010 LSR)153.175 124 R 19.17(#c for)2.5 F 2.5(c!) 2.5 G 10 2.5(=0 L)-2.5 H(ogical Shift Right)-2.5 E(LSR #32)183.175 136 Q (for c)16.11 E 2.5(=0)5 G 12.5(011 LSR)153.175 148 R 72.57(Rc Logical) 2.5 F(Shift Right)2.5 E 12.5(100 ASR)153.175 160 R 18.06(#c for)2.5 F 2.5(c!)2.5 G 10 2.5(=0 A)-2.5 H(rithmetic Shift Right)-2.5 E(ASR #32) 183.175 172 Q(for c)15 E 2.5(=0)5 G 12.5(101 ASR)153.175 184 R 71.46 (Rc Arithmetic)2.5 F(Shift Right)2.5 E 12.5(110 R)153.175 196 R(OR #c) -.4 E(for c != 0)19.85 E(Rotate Right.)17.5 E 28.89(RRX for)183.175 208 R 5(c=)2.5 G 18.33(0R)-2.5 G(otate Right one bit with e)-18.33 E(xtend.) -.15 E 12.5(111 R)153.175 220 R(OR Rc)-.4 E(Rotate Right)73.25 E 427.825 224.5 148.175 224.5 DL 427.825 76.5 427.825 224.5 DL 148.175 76.5 148.175 224.5 DL .381(In the re)72 241.6 R .381(gister form, Rc is sign\ i\214ed by bits 8-11; bit 7 must be clear if Rc is used. \(If you code \ a 1 instead,)-.15 F(you')72 253.6 Q(ll get a multiply)-.1 E 2.5(,aS)-.65 G(WP or something unallocated instead of a data processing instruction.\ \))-2.5 E(Also, only the bottom byte of Rc is used \212 If Rc = 256, th\ en the shifts will be by zero.)72 269.2 Q("MO)72 284.8 Q 1.18(V[S] Ra,R\ b,RLX" can be done by ADC[S] Ra,Rb,Rb, with RLX meaning Rotate Left one\ bit with)-.5 F -.15(ex)72 296.8 S(tend.).15 E .382 (Most assemblers allo)72 312.4 R 2.881(wA)-.25 G .381 (SL to be used as a synon)-2.881 F .381(ym for LSL. Since opinions dif) -.15 F .381(fer on what an arithmetic)-.25 F (left shift is, LSL is the preferred term.)72 324.4 Q .838 (By setting the S bit in a MO)72 340 R 3.418 -1.29(V, M)-.5 H .838 (VN or logical instruction, \(in either the re)1.29 F .838 (gister or immediate form\) the)-.15 F (carry \215ag is set to be the last bit shifted out.)72 352 Q (If no shift is done, the carry \215ag will be unaf)72 367.6 Q(fected.) -.25 E .863(If there is a choice of forms for an immediate \(e.g. #1 co\ uld be represented as 1 R)72 383.2 R .863(OR #0, 4 R)-.4 F .863 (OR #2, 16)-.4 F -.4(RO)72 395.2 S 2.883(R#).4 G 2.883(4o)-2.883 G 2.883 (r6)-2.883 G 2.883(4R)-2.883 G .383(OR #6\), the assembler is e)-3.283 F .383(xpected to use the one in)-.15 F -.2(vo)-.4 G .383 (lving a zero rotation, if a).2 F -.25(va)-.2 G .383(ilable. So).25 F (MO)72 407.2 Q(VS Rn,#const will lea)-.5 E .3 -.15(ve t)-.2 H (he carry \215ag unaf).15 E(fected if 0 <= const <= 255, b)-.25 E (ut will change it otherwise.)-.2 E 439.01 421.3 136.99 421.3 DL 13.62 (aaaa Assembler)143.11 430.8 R 60.69(Meaning P-Code)15 F 439.01 435.3 136.99 435.3 DL 12.5(0000 AND)141.99 444.8 R(Boolean And)36.11 E (Rd = Rn AND Op2)45.69 E 12.5(0001 EOR)141.99 456.8 R(Boolean Eor)37.77 E(Rd = Rn EOR Op2)48.47 E 12.5(0010 SUB)141.99 468.8 R 62.91 (Subtract Rd)38.32 F 2.5(=R)2.5 G 5(n-O)-2.5 G(p2)-5 E 12.5(0011 RSB) 141.99 480.8 R(Re)38.87 E -.15(ve)-.25 G(rse Subtract).15 E(Rd = Op2 -) 31.1 E(Rn)5 E 12.5(0100 ADD)141.99 492.8 R 60.68(Addition Rd)36.11 F 2.5 (=R)2.5 G 5(n+O)-2.5 G(p2)-5 E 12.5(0101 ADC)141.99 504.8 R (Add with Carry)36.66 E(Rd = Rn)35.97 E 5(+O)5 G(p2 + C)-5 E 12.5 (0110 SBC)141.99 516.8 R(Subtract with carry)38.87 E(Rd = Rn)22.09 E 5 (-O)5 G(p2 - \(1-C\))-5 E 12.5(0111 RSC)141.99 528.8 R(Re)38.87 E -.15 (ve)-.25 G(rse sub w/carry).15 E(Rd = Op2 -)17.5 E 2.5(Rn -)5 F(\(1-C\)) 2.5 E 12.5(1000 TST)141.99 540.8 R -.7(Te)39.99 G(st bit).7 E (Rn AND Op2)69.16 E 12.5(1001 TEQ)141.99 552.8 R -.7(Te)38.33 G (st equality).7 E(Rn EOR Op2)47.5 E 12.5(1010 CMP)141.99 564.8 R 59.58 (Compare Rn)36.65 F 5(-O)5 G(p2)-5 E 12.5(1011 CMN)141.99 576.8 R (Compare Ne)34.99 E -.05(ga)-.15 G(ti).05 E 21.88 -.15(ve R)-.25 H 5(n+) .15 G(Op2)-2.5 E 12.5(1100 ORR)141.99 588.8 R(Boolean Or)37.21 E (Rd = Rn OR)52.36 E(Op2)5 E 12.5(1101 MO)141.99 600.8 R 34.94(VM)-.5 G .3 -.15(ove v)-34.94 H 49.3(alue Rd)-.1 F 20(=O)2.5 G(p2)-20 E 12.5 (1110 BIC)141.99 612.8 R(Bit clear)41.1 E(Rd = Rn AND NO)64.58 E 2.5(TO) -.4 G(p2)-2.5 E 12.5(1111 MVN)141.99 624.8 R(Mo)34.44 E .3 -.15(ve N) -.15 H 55.71(ot Rd).15 F 10(=N)2.5 G .8 -.4(OT O)-10 H(p2).4 E 439.01 629.3 136.99 629.3 DL 439.01 421.3 439.01 629.3 DL 136.99 421.3 136.99 629.3 DL .582(Note that MVN and CMN are not as related as the)72 642.8 R 3.082<798c>-.15 G .581(rst appear; MVN uses straight bitwise ne)-3.082 F -.05(ga)-.15 G .581(tion, set-).05 F(ting Rn to the 1')72 654.8 Q 2.5 (sc)-.55 G(omplement of Op2. CMN compares Rn with the 2')-2.5 E 2.5(sc) -.55 G(omplement of Op2.)-2.5 E(These instructions f)72 670.4 Q (all broadly into 4 subsets:)-.1 E(MO)72 686 Q 2.58 -1.29(V, M)-.5 H(VN) 1.29 E .47(Rn is ignored, and should be 0000. If the S bit is set, N an\ d Z are set on the result, and if the shifter is)87 698 R (used, C is set to be the last bit shifted out. V is unaf)87 710 Q (fected.)-.25 E EP %%Page: 7 7 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-7-)282.17 48 Q(CMN, CMP)72 84 Q 2.5(,T)-1.11 G (EQ, TST)-2.5 E 1.072(Rd is not set by the instruction, and should be 0\ 000. The S bit must be set \(most assemblers do this)87 96 R (automatically; if it weren')87 108 Q 2.5(ts)-.18 G (et, the instruction w)-2.5 E (ould be MRS, MSR, or an unallocated one.\))-.1 E(The arithmetic operat\ ions \(CMN, CMP\) set N, Z on result, and C and V from the ALU.)87 132 Q .56(The logical operations \(TEQ, TST\) set N and Z on the result, C fr\ om the shifter if it is used \(in which)87 156 R (case it becomes the last bit shifted out\), and V is unaf)87 168 Q (fected.)-.25 E .705(As a special case \(for ARMs >= 6, this only appli\ es to 26 bit code\), the dddd \214eld being 1111 causes)87 192 R .04 (\215ags \(in user mode\), or the entire 26 bit PSR \(in pri)87 204 R (vile)-.25 E .041(ged modes\) to be set from the corresponding bits)-.15 F .76(of the result. This is indicated by a P suf)87 216 R .76 (\214x to the instruction \212 CMNP)-.25 F 3.26(,C)-1.11 G(MPP)-3.26 E 3.26(,T)-1.11 G(EQP)-3.26 E 3.26(,T)-1.11 G(STP)-3.26 E 3.26(.T)-1.11 G .76(his is)-3.26 F 1.78 (most commonly used to change mode via TEQP PC,#\(ne)87 228 R 4.281(wm) -.25 G 1.781(ode number\). In 32 bit modes, MSR)-4.281 F (should be used instead \(as TEQP etc will not w)87 240 Q(ork\).)-.1 E (ADC, ADD, RSB, RSC, SBC, SUB)72 255.6 Q(If the S bit is set, then N an\ d Z are set on result, and C and V are set from the ALU.)87 267.6 Q (AND, BIC, EOR, ORR)72 283.2 Q 1.271(If the S bit is set, then N and Z \ are set on result, C is set from the shifter if used \(in which case it) 87 295.2 R(becomes the last bit shifted out\) and V is unaf)87 307.2 Q (fected.)-.25 E 2.03(ADD and SUB can be used to mak)72 322.8 R 4.53(er) -.1 G -.15(eg)-4.53 G 2.03 (isters point to data in a position independent w).15 F(ay)-.1 E 4.53 (,e)-.65 G 2.03(g. ADD)-4.68 F .193 (R0,PC,#24. This is so useful that some assemblers ha)72 334.8 R .493 -.15(ve a s)-.2 H .193(pecial directi).15 F .493 -.15(ve c)-.25 H .193 (alled ADR which generates the).15 F .012 (appropriate ADD or SUB automatically)72 346.8 R 2.512(.\()-.65 G .013 (ADR R0, fred typically puts the address of fred into R0, assuming) -2.512 F(fred is within range\).)72 358.8 Q (In 26-bit modes, special cases occur when R15 is one of the re)72 374.4 Q(gisters being used:)-.15 E 21.5<8349>72 390 S 2.5(fR)-21.5 G 2.5(n=R) -2.5 G(15 then the v)-2.5 E(alue used is R15 with all the PSR bits mask) -.25 E(ed out.)-.1 E 21.5<8349>72 405.6 S 2.5(fO)-21.5 G(p2 in)-2.5 E -.2(vo)-.4 G(lv).2 E(es R15, then all 32 bits are used.)-.15 E (In 32-bit modes, all the bits of R15 are used.)72 421.2 Q (In 26-bit modes, if Rd = R15 then:)72 436.8 Q 21.5<8349>72 452.4 S 2.5 (ft)-21.5 G(he S bit is not set, only the 24 bits of the PC are set.) -2.5 E 21.5<8349>72 468 S 3.388(ft)-21.5 G .888 (he S bit is set, both the PC and PSR are o)-3.388 F -.15(ve)-.15 G .887 (rwritten \(though the Mode, I and F bits will not be).15 F (altered unless we are in a non-user mode.\))97 480 Q -.15(Fo)72 495.6 S 3.003(r3).15 G .504 (2-bit modes, if Rd=15, all the bits of the PC will be o)-3.003 F -.15 (ve)-.15 G .504(rwritten, e).15 F .504(xcept the tw)-.15 F 3.004(ol)-.1 G .504(east signi\214cant bits,)-3.004 F .009(which are al)72 507.6 R -.1(wa)-.1 G .008(ys zero.).1 F .008(If the S bit is not set, that is a\ ll that happens; if the S bit is set, the SPSR for the cur)5.008 F(-)-.2 E .063(rent mode is copied to the CPSR. Y)72 519.6 R .063 (ou should not e)-1.1 F -.15(xe)-.15 G .063 (cute a data processing instruction with the PC as desti-).15 F 1.075(n\ ation and the S bit set in 32-bit user mode, since user mode does not h\ a)72 531.6 R 1.375 -.15(ve a)-.2 H 3.574(nS).15 G 1.074(PSR. \(By the w) -3.574 F(ay)-.1 E 3.574(,y)-.65 G(ou)-3.574 E -.1(wo)72 543.6 S(n').1 E 2.791(tb)-.18 G .291(reak the processor by doing so \212 it')-2.791 F 2.791(sj)-.55 G .291(ust that the results of doing so aren')-2.791 F 2.791(td)-.18 G .291(e\214ned, and may dif)-2.791 F(fer)-.25 E (between processors.\))72 555.6 Q .058(These instructions tak)72 571.2 R 2.558(et)-.1 G .058(he follo)-2.558 F .058(wing number of c)-.25 F .058 (ycles to e)-.15 F -.15(xe)-.15 G .057(cute: 1S + \(1S if re).15 F .057 (gister controlled shift used\))-.15 F 2.5(+\()72 583.2 S (1S + 1N if PC changed\))-2.5 E/F1 10/Times-Bold@0 SF 2.5(5.3. Branch)72 610.8 R(Instructions)2.5 E/F2 9/Courier@0 SF (xxxx101L oooooooo oooooooo oooooooo)72 636.4 Q F0 -.8(Ty)72 664 S (pical Assembler Syntax:).8 E F2 5.4(BEQ address)115.2 696 R (BLNE subroutine)115.2 706 Q EP %%Page: 8 8 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-8-)282.17 48 Q .397 (These instructions are used to force a jump to a ne)72 84 R 2.897(wa) -.25 G .397(ddress, gi)-2.897 F -.15(ve)-.25 G 2.897(na).15 G 2.897(sa) -2.897 G 2.897(no)-2.897 G -.25(ff)-2.897 G .397(set in w).25 F .398 (ords from the v)-.1 F .398(alue of)-.25 F (the PC as this instruction is e)72 96 Q -.15(xe)-.15 G(cuted.).15 E .381(Due to the pipeline, the PC is al)72 111.6 R -.1(wa)-.1 G .381(ys \ 2 instructions \(8 bytes\) ahead of the address at which this instructi\ on).1 F -.1(wa)72 123.6 S 2.5(ss).1 G(tored, so a branch with of)-2.5 E (fset = \(sign e)-.25 E(xtended v)-.15 E(ersion of bits 0-23\):)-.15 E (destination address = current address + 8 + \(4 * of)191.355 141.6 Q (fset\))-.25 E(In 26-bit modes, the top 6 bits of the destination addre\ ss are cleared.)72 159.6 Q .073(If the L \215ag is set, then the curren\ t contents of PC are copied into R14 before the branch is tak)72 175.2 R .074(en. Thus R14)-.1 F(holds the address of the instruction after the \ branch, and the called routine can return with MO)72 187.2 Q 2.5(VP)-.5 G(C,R14.)-2.5 E 1.067(In 26-bit modes, using MO)72 202.8 R 1.066(VS PC,\ R14, to return from a branch with link, the PSR \215ags can be restored) -.5 F .1(automatically on return. The beha)72 214.8 R .1(viour of MO)-.2 F .1(VS PC,R14 is dif)-.5 F .1 (ferent in 32-bit modes, and only suitable for)-.25 F(return from an e) 72 226.8 Q(xception.)-.15 E(Both branch and branch with links, tak)72 242.4 Q 2.5(e2)-.1 G(S+1N c)-2.5 E(ycles to e)-.15 E -.15(xe)-.15 G (cute.).15 E/F1 10/Times-Bold@0 SF 2.5(5.4. Multiplication)72 270 R/F2 9 /Courier@0 SF(xxxx0000 00ASdddd nnnnssss 1001mmmm)72 295.6 Q F0 -.8(Ty) 72 323.2 S(pical Assembler Syntax:).8 E F2(MULEQS Rd, Rm, Rs)115.2 355.2 Q 16.2(MLA Rd,)115.2 365.2 R(Rm, Rs, Rn)5.4 E F0 .062 (These instructions multiply the v)72 392.8 R .062(alues of 2 re)-.25 F .062(gisters, and optionally add a third, placing the result in another) -.15 F(re)72 404.8 Q(gister)-.15 E(.)-.55 E(If the S bit is set, the N \ and Z \215ags are set on the result, C is unde\214ned, and V is unaf)72 420.4 Q(fected.)-.25 E(If the A bit is set, then the ef)72 436 Q (fect of the operation is Rd = Rm.Rs + Rn otherwise, Rd = Rm.Rs.)-.25 E 1.337(The destination re)72 451.6 R 1.337 (gister shall not be the same as the operand re)-.15 F 1.337(gister Rm.) -.15 F 1.338(R15 shall not be used as an)6.338 F (operand or as the destination re)72 463.6 Q(gister)-.15 E(.)-.55 E .529 (These instructions tak)72 479.2 R 3.029(e1)-.1 G 3.029(S+1)-3.029 G .529(6I c)-3.029 F .529(ycles to e)-.15 F -.15(xe)-.15 G .529 (cute in the w).15 F .529(orst case, and may be less depending on ar)-.1 F(gue-)-.18 E(ment v)72 491.2 Q(alues. The e)-.25 E (xact time depends on the v)-.15 E(alue of Rs, according to the follo) -.25 E(wing table:)-.25 E .4 LW 399.74 501.7 176.26 501.7 DL (Range of Rs)220.31 511.2 Q(Number of c)54.05 E(ycles)-.15 E 399.74 515.7 176.26 515.7 DL(&0 \212)226.26 525.2 Q 51.98(&1 1S)5 F 2.5(+1)2.5 G(I)-2.5 E(&2 \212)226.26 537.2 Q 51.98(&7 1S)5 F 2.5(+2)2.5 G(I)-2.5 E (&8 \212)226.26 549.2 Q 46.42(&1F 1S)5 F 2.5(+3)2.5 G(I)-2.5 E(&20 \212) 221.26 561.2 Q 46.42(&7F 1S)5 F 2.5(+4)2.5 G(I)-2.5 E(&80 \212)221.26 573.2 Q 40.86(&1FF 1S)5 F 2.5(+5)2.5 G(I)-2.5 E(&200 \212)216.26 585.2 Q 40.86(&7FF 1S)5 F 2.5(+6)2.5 G(I)-2.5 E(&800 \212)216.26 597.2 Q 35.3 (&1FFF 1S)5 F 2.5(+7)2.5 G(I)-2.5 E(&2000 \212)211.26 609.2 Q 35.3 (&7FFF 1S)5 F 2.5(+8)2.5 G(I)-2.5 E(&8000 \212)211.26 621.2 Q 29.74 (&1FFFF 1S)5 F 2.5(+9)2.5 G(I)-2.5 E(&20000 \212)206.26 633.2 Q 29.74 (&7FFFF 1S)5 F 2.5(+1)2.5 G(0I)-2.5 E(&80000 \212)206.26 645.2 Q 24.18 (&1FFFFF 1S)5 F 2.5(+1)2.5 G(1I)-2.5 E(&200000 \212)201.26 657.2 Q 24.18 (&7FFFFF 1S)5 F 2.5(+1)2.5 G(2I)-2.5 E(&800000 \212)201.26 669.2 Q 18.62 (&1FFFFFF 1S)5 F 2.5(+1)2.5 G(3I)-2.5 E(&2000000 \212)196.26 681.2 Q 18.62(&7FFFFFF 1S)5 F 2.5(+1)2.5 G(4I)-2.5 E(&8000000 \212)196.26 693.2 Q 13.06(&1FFFFFFF 1S)5 F 2.5(+1)2.5 G(5I)-2.5 E(&20000000 \212)191.26 705.2 Q 12.5(&FFFFFFFF 1S)5 F 2.5(+1)2.5 G(6I)-2.5 E 399.74 709.7 176.26 709.7 DL 399.74 501.7 399.74 709.7 DL 176.26 501.7 176.26 709.7 DL EP %%Page: 9 9 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-9-)282.17 48 Q 1.798 (These multiplication timings don')72 84 R 4.298(ta)-.18 G 1.798 (pply to ARM7DM. ARM7DM timings are gi)-4.298 F -.15(ve)-.25 G 4.299(nb) .15 G 4.299(yt)-4.299 G 1.799(he follo)-4.299 F(wing)-.25 E(table.)72 96 Q .4 LW 477.93 106.5 98.07 106.5 DL(MLA/)289.05 116 Q(Range of Rs) 150.325 128 Q 14.81(MUL SMULL)49.755 F 12.5(SMLAL UMULL UMLAL)15 F 477.93 132.5 98.07 132.5 DL(&0 \212)151.43 142 Q 46.41(&FF 1S+1I)5 F 21.86(1S+2I 1S+3I 1S+2I)15 F(1S+3I)26.02 E(&100 \212)141.43 154 Q 35.29 (&FFFF 1S+2I)5 F 21.86(1S+3I 1S+4I 1S+3I)15 F(1S+4I)26.02 E(&10000 \212) 131.43 166 Q 24.17(&FFFFFF 1S+3I)5 F 21.86(1S+4I 1S+5I 1S+4I)15 F(1S+5I) 26.02 E(&1000000 \212)121.43 178 Q 12.5(&FEFFFFFF 1S+4I 1S+5I)5 F 21.86 (1S+6I 1S+5I)24.36 F(1S+6I)26.02 E(&FF000000 \212)115.31 190 Q 12.5 (&FFFEFFFF 1S+3I 1S+4I)5 F 21.86(1S+5I 1S+5I)24.36 F(1S+6I)26.02 E (&FFFF0000 \212)114.19 202 Q 12.5(&FFFFFEFF 1S+2I 1S+3I)5 F 21.86 (1S+4I 1S+5I)24.36 F(1S+6I)26.02 E(&FFFFFF00 \212)113.07 214 Q 13.05 (&FFFFFFFF 1S+1I)5 F 21.86(1S+2I 1S+3I 1S+5I)15 F(1S+6I)26.02 E 477.93 218.5 98.07 218.5 DL 477.93 106.5 477.93 218.5 DL 98.07 106.5 98.07 218.5 DL/F1 10/Times-Bold@0 SF 2.5(5.5. Long)72 247.6 R (Multiplication \(ARM7DM\))2.5 E/F2 9/Courier@0 SF (xxxx0000 1UAShhhh llllssss 1001mmmm)72 273.2 Q F0 -.8(Ty)72 300.8 S (pical Assembler Syntax:).8 E F2 5.4(UMULL Rl,Rh,Rm,Rs)115.2 332.8 R 5.4 (UMLAL Rl,Rh,Rm,Rs)115.2 342.8 R 5.4(SMULL Rl,Rh,Rm,Rs)115.2 352.8 R 5.4 (SMLAL Rl,Rh,Rm,Rs)115.2 362.8 R F0(These instructions multiply the v)72 390.4 Q(alues of re)-.25 E (gisters Rm and Rs to obtain a 64-bit product.)-.15 E 2.155(When the U \ bit is clear the multiply is unsigned \(UMULL or UMLAL\), otherwise sig\ ned \(SMULL,)72 406 R 2.502(SMLAL\). When)72 418 R .003(the A bit is cl\ ear the result is stored with its least signi\214cant half in Rl and it\ s most signi\214-)2.502 F(cant half in Rh.)72 430 Q (When A is set, the result is instead added to the contents of Rh,Rl.)5 E(The program counter)72 445.6 Q 2.5(,R)-.4 G(15 should not be used.) -2.5 E(Rh, Rl and Rm should be dif)5 E(ferent.)-.25 E(If the S bit is s\ et, the N and Z \215ags are set on the 64-bit result, C and V are unde\ \214ned.)72 461.2 Q -.35(Ti)72 476.8 S(mings for these can be found abo) .35 E .3 -.15(ve i)-.15 H 2.5(nt).15 G(he multiplication section.)-2.5 E F1 2.5(5.6. Single)72 510.4 R(Data T)2.5 E(ransfer)-.74 E F2 (xxxx010P UBWLnnnn ddddoooo oooooooo)72 536 Q(Immediate form)10.8 E (xxxx011P UBWLnnnn ddddcccc ctt0mmmm)72 546 Q(Register form)10.8 E F0 -.8(Ty)72 573.6 S(pical Assembler Syntax:).8 E F2 5.4(LDR Rd,)115.2 605.6 R([Rn, Rm, ASL#1]!)5.4 E 5.4(STR Rd,)115.2 615.6 R([Rn],#2)5.4 E (LDRT Rd, [Rn])115.2 625.6 Q(LDRB Rd, [Rn])115.2 635.6 Q F0 .519 (These instructions load/store a w)72 663.2 R .518 (ord of memory from/to a re)-.1 F(gister)-.15 E 3.018(.T)-.55 G .518 (he \214rst re)-3.018 F .518(gister used in specifying the)-.15 F (address is termed the base re)72 675.2 Q(gister)-.15 E(.)-.55 E (If the L bit is set, then a load is performed. If not, a store.)72 690.8 Q(If the P bit is set, then Pre-inde)72 706.4 Q -.15(xe)-.15 G 2.5 (da).15 G(ddressing is used, otherwise post-inde)-2.5 E -.15(xe)-.15 G 2.5(da).15 G(ddressing is used.)-2.5 E EP %%Page: 10 10 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-10-)279.67 48 Q (If the U bit is set, then the of)72 84 Q(fset gi)-.25 E -.15(ve)-.25 G 2.5(ni).15 G 2.5(sa)-2.5 G(dded to the base re)-2.5 E (gister \212 otherwise it is subtracted.)-.15 E .341(If the B bit is se\ t, then a byte of memory is transferred, otherwise a w)72 99.6 R .341 (ord is transferred. This is signi\214ed to)-.1 F (assemblers by post\214xing the mnemonic stub with a `B'.)72 111.6 Q (The interpretation of the W bit depends on the addressing mode used:)72 127.2 Q 21.5<8346>72 142.8 S 1.426(or pre-inde)-21.65 F -.15(xe)-.15 G 3.926(da).15 G 1.426(ddressing, W being set forces the writing back of \ the \214nal address used for the)-3.926 F .104 (address translation into the base re)97 154.8 R(gister)-.15 E 2.605 (.\()-.55 G 2.605(i.e. A)-2.605 F .105(side ef)2.605 F .105 (fect of the transfer is Rn := Rn +/- of)-.25 F .105(fset. This)-.25 F (is signi\214ed to assemblers by post\214xing the instruction with !.\)) 97 166.8 Q 21.5<8346>72 182.4 S .792(or post-inde)-21.65 F -.15(xe)-.15 G 3.292(da).15 G .792(ddressing, the address is al)-3.292 F -.1(wa)-.1 G .791(ys written back, and the bit being set indicates that).1 F .219 (an address translation should be forced before the transfer tak)97 194.4 R .22(es place. This is signi\214ed to assmeblers)-.1 F (by post\214xing the mnemonic stub with `T'.)97 206.4 Q .04(An address \ translation causes the chip to tell the memory system that this is a us\ er mode transfer)72 222 R 2.54(,r)-.4 G -2.25 -.15(eg a)-2.54 H(rdless) .15 E 1.095(of whether the chip is in a user mode or a pri)72 234 R (vile)-.25 E 1.096 (ged mode at the time. This is useful e.g. when writing)-.15 F .548 (emulators: suppose for instance that a user mode program e)72 246 R -.15(xe)-.15 G .548(cutes an STF instruction to an area of mem-).15 F .324(ory that may not be written by user mode code. If this is e)72 258 R -.15(xe)-.15 G .324(cuted by an FP).15 F .325 (A, it will abort. If it is e)-.92 F -.15(xe)-.15 G(cuted).15 E .463 (by the FPE, it should also abort. But the FPE runs in a pri)72 270 R (vile)-.25 E .463(ged mode, so if it were to use normal stores,)-.15 F (the)72 282 Q 3.661(yw)-.15 G(ouldn')-3.761 E 3.661(ta)-.18 G 1.161 (bort. T)-3.661 F 3.661(om)-.8 G(ak)-3.661 E 3.661(ea)-.1 G 1.161 (borts w)-3.661 F 1.162(ork properly)-.1 F 3.662(,i)-.65 G 3.662(ti) -3.662 G 1.162(nstead uses normal stores if it w)-3.662 F 1.162 (as called from a)-.1 F(pri)72 294 Q(vile)-.25 E(ged mode, b)-.15 E (ut STR)-.2 E(Ts if it w)-.6 E(as called from a user mode.)-.1 E .163 (If the immediate form of the instruction is used, the o \214eld gi)72 309.6 R -.15(ve)-.25 G 2.662(sa1).15 G .162(2-bit of)-2.662 F .162 (fset. If the re)-.25 F .162(gister form is used,)-.15 F .292(then it i\ s decoded as for the data processing instructions, with the restriction\ that shifts by re)72 321.6 R .293(gister amounts)-.15 F(are not allo)72 333.6 Q(wed.)-.25 E(If R15 is used as Rd, the PSR is not modi\214ed. Th\ e PC should not be used in Op2.)72 349.2 Q(Other restrictions:)72 364.8 Q 21.5<8344>72 380.4 S(on')-21.5 E 2.5(tu)-.18 G (se writeback or post-inde)-2.5 E(xing when the base re)-.15 E (gister is the PC.)-.15 E 21.5<8344>72 396 S(on')-21.5 E 2.5(tu)-.18 G (se the PC as Rd for an LDRB or STRB.)-2.5 E 21.5<8357>72 411.6 S .554 (hen using post-inde)-21.5 F .554(xing with a re)-.15 F .554(gister of) -.15 F .554(fset, don')-.25 F 3.054(tm)-.18 G(ak)-3.054 E 3.054(eR)-.1 G 3.054(na)-3.054 G .554(nd Rm the same re)-3.054 F .553 (gister \(doing so)-.15 F(mak)97 423.6 Q(es reco)-.1 E -.15(ve)-.15 G (ry from aborts impossible\).).15 E 2.5(Al)72 439.2 S(oad tak)-2.5 E (es 1S + 1N + 1I + \(1S + 1N if PC changed\) c)-.1 E (ycles, and a store tak)-.15 E(es 2N c)-.1 E(ycles.)-.15 E/F1 10 /Times-Bold@0 SF 2.5(5.7. Block)72 466.8 R(Data T)2.5 E(ransfer)-.74 E /F2 9/Courier@0 SF(xxxx100P USWLnnnn llllllll llllllll)72 492.4 Q F0 -.8 (Ty)72 520 S(pical Assembler Syntax:).8 E F2 10.8(LDMFD Rn!,)115.2 552 R ({R0-R4, R8, R12})5.4 E(STMEQIA Rn,)115.2 562 Q({R0-R3})16.2 E 10.8 (STMIB Rn, {R0-R3}^)115.2 572 R F0 .202 (These instructions are used to load/store lar)72 599.6 R .202 (ge numbers of re)-.18 F .202 (gisters from/to memory at a time. The memory)-.15 F 1.527 (addresses used are either increasing or decreasing in memory from a v) 72 611.6 R 1.527(alue held in a base re)-.25 F(gister)-.15 E 4.027(,R) -.4 G(n,)-4.027 E .363(\(which may itself be stored\), and the \214nal \ address can be written back into the base. These instructions are)72 623.6 R .902(ideal for implementing stacks, and storing/restoring the c\ ontents of re)72 635.6 R .902(gisters on entry/e)-.15 F .902 (xit from a subrou-)-.15 F(tine.)72 647.6 Q(The U bit indicates whether\ the address will be modi\214ed by +4 \(set\), or -4 \(clear\) for each\ re)72 663.2 Q(gister)-.15 E(.)-.55 E(The W bit al)72 678.8 Q -.1(wa)-.1 G(ys indicates writeback.).1 E(If set, the L bit indicates a load opera\ tion should be performed. If clear)72 694.4 Q 2.5(,as)-.4 G -2.25 -.2 (av e)-2.5 H(.).2 E .5(The P bit is used indicate whether to increment/\ decrement the base before or after each load/store \(see the)72 710 R (table belo)72 722 Q(w\).)-.25 E EP %%Page: 11 11 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-11-)279.67 48 Q (Bit l is set if Rl is to be loaded/stored by this operation.)72 84 Q .729(Assemblers typically follo)72 99.6 R 3.229(wt)-.25 G .729 (he mnemonic stub with a condition code, and then a tw)-3.229 F 3.229 (ol)-.1 G .728(etter code to indi-)-3.229 F (cate the settings of the U and W bits.)72 111.6 Q .4 LW 406.315 122.1 169.685 122.1 DL 12.5(Stub Meaning)174.685 131.6 R 15(PU)129.96 G 406.315 136.1 169.685 136.1 DL 17.6 -.4(DA D)174.685 145.6 T (ecrement Rn After each store/load).4 E 15.56(00)21.11 G 16.95 (DB Decrement)174.685 157.6 R(Rn Before each store/load)2.5 E 15.56(10) 15 G 20.29(IA Increment)174.685 169.6 R(Rn After each store/load)2.5 E 15.56(01)24.44 G 20.84(IB Increment)174.685 181.6 R (Rn Before each store/load)2.5 E 15.56(11)18.33 G 406.315 186.1 169.685 186.1 DL 406.315 122.1 406.315 186.1 DL 169.685 122.1 169.685 186.1 DL (Synon)72 203.2 Q(yms for these e)-.15 E (xist which are clearer when implementing stacks:)-.15 E 357.44 213.7 218.56 213.7 DL 12.5(Stub Meaning)223.56 223.2 R 357.44 227.7 218.56 227.7 DL 17.51(EA Empty)223.56 237.2 R(Ascending stack)2.5 E 17.51 (ED Empty)223.56 249.2 R(Decending stack)2.5 E 20.28 -.74(FA F)223.56 261.2 T(ull Ascending stack).74 E 18.06(FD Full)223.56 273.2 R (Decending stack)2.5 E 357.44 277.7 218.56 277.7 DL 357.44 213.7 357.44 277.7 DL 218.56 213.7 218.56 277.7 DL .359 (In an empty stack, the stack pointer points to the ne)72 294.8 R .359 (xt empty position. In a full one the stack pointer points)-.15 F 1.198 (to the topmost full position. Ascending stacks gro)72 306.8 R 3.698(wt) -.25 G -2.1 -.25(ow a)-3.698 H 1.198 (rds high locations, and descending stacks gro).25 F(w)-.25 E(to)72 318.8 Q -.1(wa)-.25 G(rds lo).1 E 2.5(wl)-.25 G(ocations.)-2.5 E 1.134 (The re)72 334.4 R 1.134(gisters are al)-.15 F -.1(wa)-.1 G 1.134 (ys stored so that the lo).1 F 1.134(west numbered re)-.25 F 1.134 (gister is at the lo)-.15 F 1.135(west address in memory)-.25 F(.)-.65 E .226(This can af)72 346.4 R .226(fect stacking and unstacking code. F) -.25 F .226(or instance, if I w)-.15 F .225 (ant to push R1-R4 on to a stack, then load)-.1 F(them back tw)72 358.4 Q 2.5(oa)-.1 G 2.5(tat)-2.5 G(ime, to get them back to the same re)-2.5 E(gisters, I need to do something lik)-.15 E(e:)-.1 E/F1 9/Courier@0 SF (STMFD R13!,{R1,R2,R3,R4})88.2 390.4 Q (;Puts R1 low in memory, i.e. at end of stack)10.8 E(LDMFD R13!,{R1,R2}) 88.2 400.4 Q(LDMFD R13!,{R3,R4})88.2 410.4 Q F0 (for a descending stack, b)72 444.4 Q(ut something lik)-.2 E(e:)-.1 E F1 (STMFA R13!,{R1,R2,R3,R4})88.2 476.4 Q (;Puts R4 high in memory, i.e. at end of stack)10.8 E (LDMFA R13!,{R3,R4})88.2 486.4 Q(LDMFA R13!,{R1,R2})88.2 496.4 Q F0 (for an ascending stack.)72 530.4 Q(The codes are synon)72 546 Q (yms as follo)-.15 E(ws:)-.25 E 339.385 556.5 236.615 556.5 DL 12.5 (Code Load Store)241.615 566 R 339.385 570.5 236.615 570.5 DL 19.72 (EA DB)245.505 580 R(IA)23.61 E 21.665(ED IB)245.505 592 R -.4(DA)23.81 G 21.77 -.74(FA D)246.15 604 T 23.81(AI).34 G(B)-23.81 E 21.665(FD IA) 245.78 616 R(DB)23.61 E 339.385 620.5 236.615 620.5 DL 339.385 556.5 339.385 620.5 DL 236.615 556.5 236.615 620.5 DL .502 (The S bit controls tw)72 634 R 3.002(os)-.1 G .502(pecial functions, b\ oth of which are indicated to the assembler by putting "^" at the)-3.002 F(end of the instruction:)72 646 Q 21.5<8349>72 661.6 S 2.5(ft)-21.5 G (he S bit is set, the instruction is LDM and R15 is in the re)-2.5 E (gister list, then:)-.15 E 20(*I)72 677.2 S 2.5(n2)-20 G(6-bit pri)-2.5 E(vile)-.25 E(ged modes, all 32 bits of R15 will be loaded.)-.15 E 20 (*I)72 692.8 S 3.409(n2)-20 G .909 (6-bit user mode, the 4 \215ags and 24 PC bits of R15 will be loaded.) -3.409 F .908(Bits 27, 26, 1 and 0 of the)5.909 F(loaded v)97 704.8 Q (alue will be ignored.)-.25 E EP %%Page: 12 12 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-12-)279.67 48 Q 20(*I)72 84 S 3.308(n3)-20 G .809(2-bit modes, all 32 bits of R15 will be loaded, though note that t\ he tw)-3.308 F 3.309(ob)-.1 G .809(ottom bits are al)-3.309 F -.1(wa)-.1 G(ys).1 E .554(zero, so an)97 96 R 3.054(yo)-.15 G .554(nes loaded to t\ hem will be ignored. In addition, the SPSR of the current mode will be) -3.054 F .433(transferred to the CPSR; since user mode does not ha)97 108 R .733 -.15(ve a)-.2 H 2.933(nS).15 G .433 (PSR, this type of instruction should not)-2.933 F (be used in 32-bit user mode.)97 120 Q 21.5<8349>72 135.6 S 3.621(ft) -21.5 G 1.121(he S bit is set and either the instruction is STM or R15 \ is not in the re)-3.621 F 1.121(gister list, then the user)-.15 F 1.37 (mode re)97 147.6 R 1.371(gisters will be transferred rather than those\ for the current mode. This type of instruction)-.15 F (should not be used in user mode.)97 159.6 Q (Special cases occur when the base re)72 175.2 Q (gister is used in the list of re)-.15 E(gisters to be transferred.)-.15 E 21.5<8354>72 190.8 S .77(he base re)-21.5 F .77(gister can al)-.15 F -.1(wa)-.1 G .769(ys be loaded without an).1 F 3.269(yp)-.15 G 3.269 (roblems. Ho)-3.269 F(we)-.25 E -.15(ve)-.25 G 1.569 -.4(r, d).15 H(on') .4 E 3.269(ts)-.18 G .769(pecify writeback if)-3.269 F 1.104 (the base re)97 202.8 R 1.104(gister is being loaded \212 you can')-.15 F 3.604(te)-.18 G 1.105(nd up with both a written-back v)-3.604 F 1.105 (alue and a loaded)-.25 F -.25(va)97 214.8 S(lue in the base re).25 E (gister!)-.15 E 21.5<8354>72 230.4 S(he base re)-21.5 E(gister can be s\ tored with no complications as long as writeback is not used.)-.15 E 21.5<8353>72 246 S .562(toring a list of re)-21.5 F .562 (gisters including the base re)-.15 F .562 (gister using writeback will write the v)-.15 F .561(alue of the base) -.25 F(re)97 258 Q 1.168 (gister before writeback to memory only if the base re)-.15 F 1.168 (gister is the \214rst in the list. Otherwise, the)-.15 F -.25(va)97 270 S(lue which is used is not de\214ned.).25 E(Further special cases occur\ if the program counter is present in the list of re)72 285.6 Q (gisters to load and sa)-.15 E -.15(ve)-.2 G(.).15 E 21.5<8354>72 301.2 S .528(he PSR is al)-21.5 F -.1(wa)-.1 G .528(ys sa).1 F -.15(ve)-.2 G 3.028(dw).15 G .527(ith the PC \(in 26 bit modes\) \(and the PC will al) -3.028 F -.1(wa)-.1 G .527(ys be 12 bytes further).1 F (on, rather than the usual 8 \(in all modes\)\).)97 313.2 Q 21.5<834f>72 328.8 S 3.311(nal)-21.5 G .811(oad, only the bits of the PSR that are a\ lterable in the current mode can be af)-3.311 F .811(fected, and then) -.25 F(only if the S bit is set.)97 340.8 Q (The PC should not be used as the base re)72 356.4 Q(gister)-.15 E(.) -.55 E 2.518(Ab)72 372 S .018(lock data load, tak)-2.518 F .018 (es nS + 1N + 1I + \(1S + 1N if PC changed\) c)-.1 F .017 (ycles, and a block data store tak)-.15 F .017(es \(n-1\)S)-.1 F 2.5(+2) 72 384 S 2.5(Nc)-2.5 G(ycles, where "n" is the number of w)-2.65 E (ords being transferred.)-.1 E/F1 10/Times-Bold@0 SF 2.5(5.8. Softwar)72 411.6 R 2.5(ei)-.18 G(nterrupt)-2.5 E/F2 9/Courier@0 SF (xxxx1111 yyyyyyyy yyyyyyyy yyyyyyyy)72 437.2 Q F0 -.8(Ty)72 464.8 S (pical Assembler Syntax:).8 E F2 10.8(SWI "OS_WriteI")109.8 496.8 R (SWINE &400C0)109.8 506.8 Q F0 .901(On encountering a softw)72 534.4 R .902(are interrupt, the ARM switches into SVC mode, sa)-.1 F -.15(ve)-.2 G 3.402(st).15 G .902(he current v)-3.402 F .902(alue of R15)-.25 F .242 (into R14_SVC, and jumps to location 8 in memory)72 546.4 R 2.742(,w) -.65 G .241(here it assumes it will \214nd a SWI handling routine to) -2.742 F .555(decode the lo)72 558.4 R .555 (wer 24 bits of the SWI just e)-.25 F -.15(xe)-.15 G .555 (cuted, and do whate).15 F -.15(ve)-.25 G 3.055(rt).15 G .555 (he SWI number concerned means on)-3.055 F (that particular operating system.)72 570.4 Q 1.238 (An operating system written on the ARM will typically use SWIs to pro) 72 586 R 1.238(vide miscellaneous routines for)-.15 F(programmers.)72 598 Q 3.634(AS)72 613.6 S 1.134(WI tak)-3.634 F 1.134(es 2S + 1N c)-.1 F 1.135(ycles to e)-.15 F -.15(xe)-.15 G 1.135(cute \(plus whate).15 F -.15(ve)-.25 G 3.635(rt).15 G 1.135 (ime is required to decode the SWI number and)-3.635 F -.15(exe)72 625.6 S(cute the appropriate routines\).).15 E F1 2.5(5.9. Co-pr)72 653.2 R (ocessor data operations)-.18 E F2(xxxx1110 oooonnnn ddddpppp qqq0mmmm) 72 678.8 Q F0 -.8(Ty)72 706.4 S(pical Assembler Syntax:).8 E EP %%Page: 13 13 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-13-)279.67 48 Q/F1 9/Courier@0 SF (CDP p, o, CRd, CRn, CRm, q)109.8 82 Q(CDP p, o, CRd, CRn, CRm)109.8 92 Q F0 .659(This instruction is passed on to co-processor p, telling it t\ o perform operation o, on co-processor re)72 119.6 R(gisters)-.15 E (CRn and CRm, and place the result into Crd.)72 131.6 Q (qqq may supply additional information about the operation concerned.)72 147.2 Q .394(The e)72 162.8 R .394(xact meaning of these instructions d\ epends on the particular co-processor in use; The abo)-.15 F .694 -.15 (ve i)-.15 H 2.895(so).15 G .395(nly a)-2.895 F .256 (recommended usage for the bits \(and indeed the FP)72 174.8 R 2.756(Ad) -.92 G(oesn')-2.756 E 2.756(tc)-.18 G .255 (onform to it\). The only part which is oblig)-2.756 F(a-)-.05 E .563(t\ ory is that pppp must be the coprocessor number: the coprocessor design\ er is free to allocate oooo, nnnn,)72 186.8 R (dddd, qqq and mmmm as desired.)72 198.8 Q .144 (If the coprocessor uses the bits in a dif)72 214.4 R .144(ferent w)-.25 F .144(ay than the recommended one, assembler macros will proba-)-.1 F .829(bly be needed to translate the instruction syntax that mak)72 226.4 R .83(es sense to people into the correct CDP instruc-)-.1 F .005 (tion. F)72 238.4 R .005(or commonly used coprocessors such as the FP) -.15 F .004(A, man)-.92 F 2.504(ya)-.15 G .004(ssemblers ha)-2.504 F .304 -.15(ve t)-.2 H .004(he e).15 F .004(xtra mnemonics b)-.15 F .004 (uilt in)-.2 F .8(and do this translation automatically)72 250.4 R 3.3 (.\()-.65 G -.15(Fo)-3.3 G 3.3(re).15 G .8 (xample, assembling MUFEZ F0,F1,#10 as its equi)-3.45 F -.25(va)-.25 G .8(lent CDP).25 F(1,1,CR0,CR9,CR15,3.\))72 262.4 Q (Currently de\214ned co-processor numbers include:)72 278 Q .4 LW 352.73 288.5 223.27 288.5 DL 2.5(1a)228.27 298 S(nd 2)-2.5 E (Floating Point unit)15 E 31.94(15 Cache)228.27 310 R(Controller)2.5 E 352.73 314.5 223.27 314.5 DL 352.73 288.5 352.73 314.5 DL 223.27 288.5 223.27 314.5 DL .698(If a call to a coprocessor is made and the coproce\ ssor does not respond \(normally becuase it isn')72 331.6 R 3.197(tt) -.18 G(here!\),)-3.197 E .363(the unde\214ned instruction v)72 343.6 R .364(ector is called \(e)-.15 F .364 (xactly as for one of the unde\214ned instructions gi)-.15 F -.15(ve) -.25 G 2.864(nl).15 G .364(ater\). This)-2.864 F (is used to transparently pro)72 355.6 Q (vide FP support on machines without an FP)-.15 E(A.)-.92 E 1.277 (These instructions tak)72 371.2 R 3.777(e1)-.1 G 3.777(S+b)-3.777 G 3.777(Ic)-3.777 G 1.277(ycles to e)-3.927 F -.15(xe)-.15 G 1.277 (cute, where b is the number of c).15 F 1.276 (ycles that the coprocessor)-.15 F .011(causes the ARM to b)72 383.2 R (usy-w)-.2 E .012(ait before it accepts the instruction: ag)-.1 F .012 (ain, this is under the coprocessor')-.05 F 2.512(sc)-.55 G(ontrol.) -2.512 E/F2 10/Times-Bold@0 SF 2.5(5.10. Co-pr)72 410.8 R (ocessor data transfer and r)-.18 E(egister transfers)-.18 E F1 (xxxx110P UNWLnnnn DDDDpppp oooooooo LDC/STC)72 436.4 Q (xxxx1110 oooLNNNN ddddpppp qqq1MMMM MRC/MCR)72 446.4 Q F0(Ag)72 474 Q (ain these depend on the particular co-processor p in use.)-.05 E 2.812 (Na)72 489.6 S .312(nd D signify co-processor re)-2.812 F .312(gister n\ umbers, n and d are ARM processor numbers. o is the co-processor)-.15 F (operation to use. M signi\214es bits the coprocessor is free to use as\ it w)72 501.6 Q(ants.)-.1 E .112(The \214rst form, denotes LDC if L=1,\ STC otherwise. The instruction beha)72 517.2 R -.15(ve)-.2 G 2.612(sl) .15 G(ik)-2.612 E 2.612(eL)-.1 G .112(DR or STR respecti)-2.612 F -.15 (ve)-.25 G(ly).15 E(,)-.65 E(in each case with an immediate of)72 529.2 Q(fset, with the follo)-.25 E(wing e)-.25 E(xceptions.)-.15 E 21.5<8354> 72 544.8 S(he of)-21.5 E (fset is 4*\(oooooooo\), not a general 12-bit constant.)-.25 E 21.5 <8349>72 560.4 S 4.111(fP)-21.5 G 1.611(=0 \(post-inde)-4.111 F 1.611(x\ ing\) is speci\214ed, W must be 1, and W being 1 just indicates that wr\ iteback is)-.15 F 1.203(required, not that the memory system should be \ told that this is a user mode transfer)97 572.4 R 3.704(.I)-.55 G (nstructions)-3.704 E(with P=0 and W=0 are reserv)97 584.4 Q (ed for future e)-.15 E(xpansion.)-.15 E 21.5<834f>72 600 S .726 (ne or more coprocessor re)-21.5 F .726 (gisters are loaded or stored. The coprocessor determines ho)-.15 F 3.225(wm)-.25 G(an)-3.225 E 3.225(ya)-.15 G(nd)-3.225 E .278(which re)97 612 R .278(gisters are to be loaded or stored from the DDDD and N bits:\ all the ARM does is transfer a)-.15 F -.1(wo)97 624 S .417(rd to or fr\ om the indicated address, then another to or from the indicated address\ + 4, then one to).1 F(or from the indicated address + 8, etc., until t\ he coprocessor tells it to stop.)97 636 Q 21.5<8342>72 651.6 S 4.018(yc) -21.5 G(on)-4.018 E -.15(ve)-.4 G 1.518 (ntion, DDDD denotes the \(\214rst\) coprocessor re).15 F 1.518 (gister to load or store and N denotes the)-.15 F 1.36(length in some w) 97 663.6 R(ay)-.1 E 3.86(,w)-.65 G 1.36(ith N=1 indicating a "long" for\ m. Coprocessor designers are free to ignore)-3.86 F(this...)97 675.6 Q 21.5<8354>72 691.2 S(he assembler syntax is along the lines of:)-21.5 E F1 16.2(LDC p,CRd,[Rn,#20])97 723.2 R(;short form \(N=0\), pre-indexed) 16.2 E EP %%Page: 14 14 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-14-)279.67 48 Q/F1 9/Courier@0 SF 10.8 (STCL p,CRd,[Rn,#-32]!)97 82 R (;long form \(N=1\), pre-indexed with writeback)5.4 E (LDCNEL p,CRd,[Rn],#-100 ;long form \(N=1\), post-indexed)97 92 Q F0 .08 (The second form denotes, MRC, if L=1, MCR otherwise.)72 119.6 R .081 (MRC transfers a coprocessor re)5.081 F .081(gister to an ARM)-.15 F(re) 72 131.6 Q(gister)-.15 E 2.826(,M)-.4 G .326(CR the other w)-2.826 F .325(ay around \(the letters may seem the wrong w)-.1 F .325 (ay around, b)-.1 F .325(ut remember that desti-)-.2 F (nations are usually written on the left in ARM assembler\).)72 143.6 Q .318(MCR transfers the contents of ARM re)72 159.2 R .318 (gister Rd to the coprocessor)-.15 F 2.818(.T)-.55 G .319 (he coprocessor is free to do whate)-2.818 F -.15(ve)-.25 G(r).15 E .907 (it w)72 171.2 R .907(ants with it based on the v)-.1 F .907(alues of t\ he ooo, dddd, qqq and MMMM \214elds, though as usual there is a)-.25 F 1.4("standard" interpretation: write it to coprocessor re)72 183.2 R 1.4 (gister CRN, using operation ooo, with possible addi-)-.15 F (tional control pro)72 195.2 Q (vided by CRM and qqq. The assembler syntax is:)-.15 E F1 10.8 (MCR p,o,Rd,CRN,CRM,q)109.8 227.2 R F0 (Rd should not be R15 for an MCR instruction.)72 254.8 Q .299 (MRC transfers a single w)72 270.4 R .299 (ord from the coprocessor and puts it in ARM re)-.1 F .299 (gister Rd. The coprocessor is free)-.15 F .335(to generate this w)72 282.4 R .335(ord in an)-.1 F 2.836(yw)-.15 G .336(ay it lik)-2.936 F .336(es using the same \214elds as for MCR, with the standard interpret\ ation)-.1 F .656(that it comes from CRN using operation ooo, with possi\ ble additional control pro)72 294.4 R .655(vided by CRM and qqq.)-.15 F (The assembler syntax is:)72 306.4 Q F1 10.8(MRC p,o,Rd,CRN,CRM,q)109.8 338.4 R F0 1.019 (If Rd is R15 for an MRC instruction, the top 4 bits of the w)72 366 R 1.019(ord transferred are used to set the \215ags; the)-.1 F 1.321(rema\ ining 28 bits are discarded. \(This is the mechanism used e.g. by \215o\ ating point comparison instruc-)72 378 R(tions.\))72 390 Q .237 (LDC and STC tak)72 405.6 R 2.737(e\()-.1 G .237(n-1\)S + 2N + bI c) -2.737 F .237(ycles to e)-.15 F -.15(xe)-.15 G .237(cute, MRC tak).15 F .237(es 1S+bI+1C c)-.1 F .237(ycles, and MCR tak)-.15 F .237(es 1S +)-.1 F 1.205(\(b+1\)I + 1C c)72 417.6 R 1.205 (ycles, where b is the number of c)-.15 F 1.204 (ycles that the coprocessor causes the ARM to b)-.15 F(usy-w)-.2 E(ait) -.1 E .092(before it accepts the instruction: ag)72 429.6 R .092 (ain, this is under the coprocessor')-.05 F 2.592(sc)-.55 G .093 (ontrol, and n is the number of w)-2.592 F(ords)-.1 E (being transferred \(Note this is under the coprocessor')72 441.6 Q 2.5 (sc)-.55 G(ontrol, not the ARM')-2.5 E(s\))-.55 E/F2 10/Times-Bold@0 SF 2.5(5.11. Single)72 469.2 R (Data Swap \(ARM 3 and later including ARM 2aS\))2.5 E F1 (xxxx0001 0B00nnnn dddd0000 1001mmmm)72 494.8 Q F0 -.8(Ty)72 522.4 S (pical Assembler Syntax:).8 E F1(SWP Rd, Rm, [Rn])109.8 554.4 Q F0 .137 (These instructions load a w)72 582 R .137(ord of memory \(address gi) -.1 F -.15(ve)-.25 G 2.637(nb).15 G 2.637(yr)-2.637 G -.15(eg)-2.637 G .137(ister Rn\) to a re).15 F .136(gister Rd and store the con-)-.15 F .527(tents of re)72 594 R .527 (gister Rm to the same address. Rm and Rd may be the same re)-.15 F (gister)-.15 E 3.027(,i)-.4 G 3.027(nw)-3.027 G .527 (hich case the contents)-3.027 F .406(of this re)72 606 R .405 (gister and of the memory location are sw)-.15 F .405 (apped. The load and store operations are lock)-.1 F .405(ed together) -.1 F .492(by setting the LOCK pin high during the operation to indicat\ e to the memory manager that the)72 618 R 2.992(ys)-.15 G .492(hould be) -2.992 F(allo)72 630 Q(wed to complete without interruption.)-.25 E(If \ the B bit is set, then a byte of memory is transferred, otherwise a w)72 645.6 Q(ord is transferred.)-.1 E(None of Rd, Rn, and Rm may be R15.)72 661.2 Q(This instruction tak)72 676.8 Q(es 1S + 2N + 1I c)-.1 E (ycles to e)-.15 E -.15(xe)-.15 G(cute.).15 E EP %%Page: 15 15 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-15-)279.67 48 Q/F1 10/Times-Bold@0 SF 2.5 (5.12. Status)72 84 R(Register transfer \(ARM 6 and later\))2.5 E/F2 9 /Courier@0 SF(xxxx0001 0s10aaaa 11110000 0000mmmm)72 109.6 Q 5.4 (MSR Register)10.8 F(form)5.4 E(xxxx0011 0s10aaaa 1111rrrr bbbbbbbb)72 119.6 Q 5.4(MSR Immediate)10.8 F(form)5.4 E (xxxx0001 0s001111 dddd0000 00000000)72 129.6 Q(MRS)10.8 E F0 -.8(Ty)72 157.2 S(pical Assembler Syntax:).8 E F2 10.8(MSR SPSR_all,)109.8 189.2 R 48.6(Rm ;aaaa)5.4 F 5.4(=1)5.4 G(001)-5.4 E 10.8(MSR CPSR_flg,)109.8 199.2 R 5.4(#&F0000000 ;aaaa)5.4 F 5.4(=1)5.4 G(000)-5.4 E (MSRNE CPSR_ctl, Rm)109.8 209.2 Q(;aaaa = 0001)54 E 10.8(MRS Rd,)109.8 219.2 R(CPSR)5.4 E F0 .567 (The s bit, when set means access the SPSR of the current pri)72 246.8 R (vile)-.25 E .567(ged mode, rather than the CPSR. This bit)-.15 F (must only be set when e)72 258.8 Q -.15(xe)-.15 G (cuting the command in a pri).15 E(vile)-.25 E(ged mode.)-.15 E (MSR is used for transfering a re)72 274.4 Q (gister or constant to a status re)-.15 E(gister)-.15 E(.)-.55 E (The aaaa bits can tak)72 290 Q 2.5(et)-.1 G(he follo)-2.5 E(wing v)-.25 E(alues:)-.25 E .4 LW 434.095 300.5 141.905 300.5 DL -1.11(Va)146.905 310 S 12.5(lue Meaning)1.11 F 434.095 314.5 141.905 314.5 DL 15.27 (0001 Set)146.905 324 R(the control bits of the PSR concerned.)2.5 E 15.27(1000 Set)146.905 336 R(the \215ag bits of the PSR concerned.)2.5 E 15.27(1001 Set)146.905 348 R (the control and \215ag bits of the PSR concerned \(i.e. all the)2.5 E (bits at present\).)184.675 360 Q 434.095 364.5 141.905 364.5 DL 434.095 300.5 434.095 364.5 DL 141.905 300.5 141.905 364.5 DL(Other v)72 378 Q (alues of aaaa are reserv)-.25 E(ed for future e)-.15 E(xpansion.)-.15 E (In the re)72 393.6 Q(gister form, the source re)-.15 E (gister is Rm. In the immediate form, the source is #b, R)-.15 E(OR #2r) -.4 E(.)-.55 E(R15 should not be speci\214ed as the source re)72 409.2 Q (gister of an MRS instruction.)-.15 E (MRS is used for transfering processor status to a re)72 424.8 Q(gister) -.15 E(.)-.55 E(The d bits store the destination re)72 440.4 Q (gister number; Rd must not be R15.)-.15 E .741(N.B. The instruction en\ codings correspond to the data processing instructions with opcodes 10x\ x \(i.e. the)72 456 R(test instructions\) and the S bit clear)72 468 Q (.)-.55 E(These instruction al)72 483.6 Q -.1(wa)-.1 G(ys e).1 E -.15 (xe)-.15 G(cute in 1-S c).15 E(ycle.)-.15 E F1 2.5(5.13. Unde\214ned)72 511.2 R(instructions)2.5 E F2 (xxxx0001 yyyyyyyy yyyyyyyy 1yy1yyyy ARM 2 only)72 536.8 Q (xxxx011y yyyyyyyy yyyyyyyy yyy1yyyy)72 546.8 Q F0 .222(These instructi\ ons are currently unde\214ned. On encountering an unde\214ned instructi\ on, the ARM switches to)72 574.4 R .505(SVC mode \(on ARM 3 and belo)72 586.4 R .506(w\) or Undef mode \(on ARM 6 and abo)-.25 F -.15(ve)-.15 G .506(\), puts the old v).15 F .506(alue of R15 into)-.25 F 1.335 (R14_SVC \(or R14_UND\) and jumps to location, where it e)72 598.4 R 1.335(xpects to \214nd code to decode the unde\214ned)-.15 F (instruction and beha)72 610.4 Q .3 -.15(ve a)-.2 H(ccordingly).15 E(.) -.65 E(Notes:)72 626 Q 21.5<8354>72 641.6 S .801 (hese instructions are documented as "unde\214ned" because the)-21.5 F 3.302(ye)-.15 G .802(nter the unde\214ned instruction pro-)-3.302 F .099 (cessor trap in this w)97 653.6 R(ay)-.1 E 2.599(.P)-.65 G .099(lenty o\ f other instructions are unde\214ned in the looser sense that nothing s\ ays)-2.599 F(what the)97 665.6 Q 2.5(yd)-.15 G(o. F)-2.5 E (or instance, bit patterns of the form:)-.15 E (xxxx0000 01xxxxxx xxxxxxxx 1001xxxx)235.5 683.6 Q 1.568(are related to\ data processing instructions, multiplies, long multiplies and SWPs, b) 97 701.6 R 1.568(ut are none of)-.2 F(these because:)97 713.6 Q EP %%Page: 16 16 %%BeginPageSetup BP %%EndPageSetup /F0 10/Times-Roman@0 SF(-16-)279.67 48 Q 20(*D)72 84 S .3 (ata processing instructions with bit 25 = 0 and bit 4 = 1 ha)-20 F .599 -.15(ve r)-.2 H -.15(eg).15 G .299(ister controlled shifts, and so must) .15 F(ha)97 96 Q .3 -.15(ve b)-.2 H(it 7 = 0.).15 E 20(*M)72 111.6 S (ultiply instructions ha)-20 E .3 -.15(ve b)-.2 H(its 23:22 = 00.).15 E 20(*L)72 127.2 S(ong multiply instructions ha)-20 E .3 -.15(ve b)-.2 H (its 23:22 = 1U.).15 E 20(*S)72 142.8 S(WPs ha)-20 E .3 -.15(ve b)-.2 H (it 24 = 1.).15 E .314(What these instructions do simply isn')72 154.8 R 2.814(td)-.18 G .314(e\214ned, whereas the ones listed abo)-2.814 F .615 -.15(ve a)-.15 H .315(re actually).15 F/F1 10/Times-Bold@0 SF(de\214ned) 2.815 E F0 .315(to enter)2.815 F(the unde\214ned instruction trap, at l\ east until some future use is found for them.)72 166.8 Q 21.5<834e>72 182.4 S 1.13(ote that the "ARM2 only" unde\214ned instructions include \ those that became SWP instructions on)-21.5 F(ARM3/ARM2as and later)97 194.4 Q(.)-.55 E F1 2.5(6. Cr)72 222 R(edits)-.18 E F0 .117 (This document w)72 237.6 R .118(as originally written by Robin W)-.1 F .118(atts, with considerable consultation with Ste)-.8 F -.15(ve)-.25 G 2.618(nS).15 G(inger)-2.618 E 2.618(.I)-.55 G(t)-2.618 E -.1(wa)72 249.6 S 2.5(st).1 G(hen later updated by Mark Smith to include more informati\ on on ARMs later than 2.)-2.5 E(Da)72 265.2 Q .42(vid Seal pro)-.2 F .42 (vided a huge list of corrections and amendments, and unwittingly pro) -.15 F .42(vided the basis for the)-.15 F (timing information in a posting to usenet.)72 277.2 Q -1.11(Va)72 292.8 S 1.405(rious corrections were also submitted/posted by Olly Betts, Cli) 1.11 F 1.706 -.15(ve J)-.25 H 1.406(ones, Alain Noullez, John V).15 F (eness,)-1.11 E(Sv)72 304.8 Q(erk)-.15 E(er W)-.1 E(iber)-.4 E 2.5(ga) -.18 G(nd Mark W)-2.5 E(ooding.)-.8 E(Thanks to e)72 320.4 Q -.15(ve) -.25 G(ryone that helped \(and if I ha).15 E .3 -.15(ve m)-.2 H (issed you here, please let me kno).15 E -.65(w.)-.25 G(\)).65 E F1 -.15 (Ju)72 336 S .752(st because I ha).15 F .952 -.1(ve i)-.25 H .752 (ncluded peoples addr).1 F .752(esses her)-.18 F .752 (e, please do not tak)-.18 F 3.252(et)-.1 G .751(his as an in)-3.252 F .751(vitation to mail)-.4 F(them any questions y)72 348 Q(ou may ha)-.25 E -.1(ve)-.25 G(!).1 E F0(Olly Betts)187.065 369.6 Q(olly@mantis.co.uk) 36.92 E -.15(Pa)187.065 381.6 S(ul Hankin).15 E(pdh13@cus.cam.ac.uk) 28.19 E(Robert Harle)187.065 393.6 Q 20.98(yr)-.15 G (obert@edu.caltech.cs)-20.98 E(Cli)187.065 405.6 Q .3 -.15(ve J)-.25 H 29.27(ones Cli).15 F -.15(ve)-.25 G(.Jones@armltd.co.uk).15 E (Alain Noullez)187.065 417.6 Q(anoullez@zig.inria.fr)21.38 E(Da)187.065 429.6 Q(vid Seal)-.2 E(
)33.8 E(Ste)187.065 441.6 Q -.15(ve)-.25 G 2.5(nS).15 G 19.83(inger s.singer@ph.surre)-2.5 F -.65(y.)-.15 G(ac.uk).65 E(Mark Smith)187.065 453.6 Q (ee91mds2@brunel.ac.uk)29.7 E(John V)187.065 465.6 Q 26.1 (eness john@uk.ac.ox.drl)-1.11 F(Robin W)187.065 477.6 Q 25.78 (atts Robin.W)-.8 F(atts@comlab)-.8 E(.ox.ac.uk)-.4 E(Sv)187.065 489.6 Q (erk)-.15 E(er W)-.1 E(iber)-.4 E 15(gs)-.18 G -.15(ve)-15 G(rk).15 E (erw@Student.csd.UU.SE)-.1 E(Mark W)187.065 501.6 Q 14.68(ooding csuo) -.8 F(v@csv)-.15 E(.w)-.65 E(arwick.ac.uk)-.1 E -.15(Fo)72 523.2 S 2.5 (rt).15 G (hose not on the internet, messages can be sent by snail mail to:)-2.5 E (Robin W)243.215 544.8 Q(atts)-.8 E(St Catherines Colle)243.215 556.8 Q (ge,)-.15 E(Oxford,)243.215 568.8 Q -.4(OX)243.215 580.8 S 2.5(13).4 G (UJ)-2.5 E EP %%Trailer end %%EOF